CRIS Current Research Information System

METRA, CECILIA
 Distribuzione geografica
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Continente #
NA - Nord America 12.699
AS - Asia 6.989
EU - Europa 5.469
AF - Africa 361
SA - Sud America 320
Continente sconosciuto - Info sul continente non disponibili 272
OC - Oceania 10
Totale 26.120
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Nazione #
US - Stati Uniti d'America 12.588
CN - Cina 2.081
SG - Singapore 1.915
GB - Regno Unito 1.465
VN - Vietnam 1.339
IT - Italia 872
DE - Germania 708
UA - Ucraina 556
HK - Hong Kong 463
SE - Svezia 452
FR - Francia 414
IN - India 390
RU - Federazione Russa 308
BR - Brasile 216
JP - Giappone 203
KR - Corea 180
IE - Irlanda 162
ZA - Sudafrica 126
EE - Estonia 95
TG - Togo 90
BG - Bulgaria 85
BD - Bangladesh 71
NL - Olanda 68
FI - Finlandia 64
TW - Taiwan 62
CI - Costa d'Avorio 61
CA - Canada 58
CH - Svizzera 52
PH - Filippine 48
AR - Argentina 43
SC - Seychelles 43
TH - Thailandia 30
MY - Malesia 28
ID - Indonesia 27
TR - Turchia 27
MX - Messico 26
PL - Polonia 26
IQ - Iraq 23
GR - Grecia 21
HR - Croazia 21
BE - Belgio 19
EC - Ecuador 17
PK - Pakistan 17
IR - Iran 15
AT - Austria 14
SA - Arabia Saudita 13
CL - Cile 12
ES - Italia 11
PE - Perù 11
PT - Portogallo 11
EG - Egitto 9
AU - Australia 8
CO - Colombia 8
DK - Danimarca 8
CZ - Repubblica Ceca 7
ET - Etiopia 7
JM - Giamaica 7
LB - Libano 7
DZ - Algeria 6
AE - Emirati Arabi Uniti 5
CR - Costa Rica 5
HU - Ungheria 5
IL - Israele 5
KE - Kenya 5
MA - Marocco 5
NO - Norvegia 5
UZ - Uzbekistan 5
AL - Albania 4
EU - Europa 4
GE - Georgia 4
PY - Paraguay 4
SI - Slovenia 4
AM - Armenia 3
BO - Bolivia 3
CY - Cipro 3
JO - Giordania 3
KG - Kirghizistan 3
KP - Corea 3
KZ - Kazakistan 3
NP - Nepal 3
RO - Romania 3
TN - Tunisia 3
VE - Venezuela 3
BB - Barbados 2
DO - Repubblica Dominicana 2
GT - Guatemala 2
HN - Honduras 2
LA - Repubblica Popolare Democratica del Laos 2
MD - Moldavia 2
NZ - Nuova Zelanda 2
OM - Oman 2
PA - Panama 2
PS - Palestinian Territory 2
RS - Serbia 2
SK - Slovacchia (Repubblica Slovacca) 2
SO - Somalia 2
UY - Uruguay 2
VC - Saint Vincent e Grenadine 2
A2 - ???statistics.table.value.countryCode.A2??? 1
AW - Aruba 1
Totale 25.839
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Città #
Ann Arbor 4.205
Singapore 1.317
Southend 1.224
Fairfield 800
Ashburn 741
Hefei 514
Wilmington 510
Chandler 505
Dallas 476
San Jose 453
Santa Clara 444
Hong Kong 416
Woodbridge 389
Jacksonville 385
Seattle 355
Ho Chi Minh City 305
Houston 305
Princeton 290
Cambridge 272
Council Bluffs 267
Beijing 249
Hanoi 248
Bologna 222
Boardman 192
Tokyo 180
Dong Ket 171
Dublin 160
Seoul 152
Lauterbourg 134
Westminster 129
Los Angeles 126
Padova 126
Nanjing 125
Berlin 98
Milan 92
Lomé 90
Medford 89
Sofia 84
Buffalo 82
Jinan 70
Mülheim 70
Shenyang 63
Saint Petersburg 62
Abidjan 60
New York 55
Bengaluru 50
Frankfurt am Main 50
Helsinki 48
San Diego 46
Da Nang 45
Shanghai 45
Hebei 44
Guangzhou 43
Bern 41
Changsha 41
Washington 40
Tianjin 37
Mahé 35
Chicago 34
Zhengzhou 33
Haiphong 31
Phoenix 31
Redondo Beach 30
Rome 29
Des Moines 27
Nanchang 27
Munich 24
São Paulo 22
Verona 22
London 21
Taipei 21
Yubileyny 21
Fremont 20
Paris 20
San Francisco 20
Montreal 19
Taiyuan 19
Lanzhou 18
Norwalk 18
Toronto 18
Amsterdam 16
Brussels 16
Hangzhou 16
Jiaxing 16
Olalla 16
Pune 16
Biên Hòa 15
Chennai 15
Qingdao 15
Atlanta 14
Brooklyn 14
Kunming 14
Mexico City 14
Nuremberg 14
Taizhou 14
Warsaw 14
Bangkok 13
Fuzhou 13
Hải Dương 13
Costa Mesa 12
Totale 18.682
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Nome #
IEEE Transactions on Emerging Topics in Computing 295
Accurate Linear Model for SET Critical Charge Estimation 267
Low Cost and High Speed Embedded Two-Rail Code Checker 262
Novel Physical Unclonable Function Implementation for Microcontrollers and Field Programmable Gate Arrays 240
Self-Checking Voter for High Speed TMR Systems 238
Model for Transient Fault Susceptibility of Combinational Circuits 238
On-Die Ring Oscillator Based Measurement Scheme for Process Parameter Variations and Clock Jitter 226
Clock Faults Induced Min and Max Delay Violations 221
New ECC for Crosstalk Effect Minimization 219
Low-Area On-Chip Circuit for Jitter Measurement in a Phase-Locked Loop 218
High-Performance Robust Latches 217
Impact of Aging Phenomena on Latches’ Robustness 217
Fault-Tolerant Inverters for Reliable Photovoltaic Systems 217
Concurrent Detection of Faults Affecting Energy Harvesting Circuits of Self-Powered Wearable Sensors 216
Faults Affecting Energy-Harvesting Circuits of Self-Powered Wireless Sensors and Their Possible Concurrent Detection 215
Early detection of photovoltaic system inverter faults 213
Implications of Clock Distribution Faults and Issues with Screening Them During Manufacturing Testing 211
Testing Resistive Opens and Bridging Faults Through Pulse Propagation 211
Power droop reduction during Launch-On-Shift scan-based logic BIST 211
Won't On-Chip Clock Calibration Guarantee Performance Boost and Product Quality? 210
AC/DC FAULT TOLERANT CODE 209
Self-Checking Monitor for NBTI Due Degradation 206
Are Our Design For Testability Features Fault Secure ? 205
Novel On-Chip Circuit for Jitter Testing in High-Speed PLLs 205
Modeling and Detection of Hotspot in Shaded Photovoltaic Cells 204
Exploiting ECC Redundancy to Minimize Crosstalk Impact 203
Low-Cost and High-Reduction Approaches for Power Droop during Launch-On-Shift Scan-Based Logic BIST 202
Multiple Transient Faults in Logic: An Issue for Next Generation ICs? 201
Low-Cost Strategy to Mitigate the Impact of Aging on Latches’ Robustness 201
Design & Test of Computers 200
Checker No-Harm Alarm Robustness 200
Checker No-Harm Alarms and Design Approaches to Tolerate Them 200
Hardware Reconfiguration Scheme for High Availability Systems 199
ACM Transactions on Design Automation of Electronic Systems 199
Intermittent and Transient Fault Diagnosis on Sparse Code Signatures 199
Error correcting code analysis for cache memory high reliability and performance 198
Impact of Aging Phenomena on Soft Error Susceptibility 198
Fast and Low-Cost Clock Deskew Buffer 197
Low Cost and Low Intrusive Approach to Test On-Line the Scheduler of High Performance Microprocessors 197
TMR voting in the presence of crosstalk faults at the voter inputs 197
Can Clock Faults Be Detected Through Functional Test ? 196
Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST 196
New Approaches for Power Binning of High Performance Microprocessors 196
Model for Thermal Behavior of Shaded Photovoltaic Cells Under Hot-Spot Condition 195
Novel Approach to Reduce Power Droop During Scan-Based Logic BIST 195
Should We Make Our Design for Testability Schemes Fault Secure ? 193
Proceedings 11th IEEE International On-Line Testing Symposium 192
Function Inherent Code Checking: A New Low Cost On-Line Testing Approach for High Performance Microprocessor Control Logic 192
Impact of Bias Temperature Instability on Soft Error Susceptibility 192
On the Selection of Unidirectional Error detecting Codes for Self-Checking Circuits' Area Overhead and Performance Optimization 190
Analysis of the Impact of Bus Implemented EDCs on On-Chip SSN 190
Fault secureness need for next generation high performance microprocessor design for testability structures 188
High-reliability Fault Tolerant Digital Systems in Nanometric Technologies: Characterization and Design Methodologies 188
Silent Data Corruption and Reliability Risks due to Faults Affecting High Performance Microprocessors’ Caches 187
Novel Approach to Clock Fault Testing for High Performance Microprocessors 187
Impact of aging on temperature measurements performed using a resistive temperature sensor with sensor-to-microcontroller direct interface 186
Load and Logic Co-Optimization for design of Soft-Error Resistant nanometer CMOS Circuits 185
Path (Min) delay Faults and Their Impact on Self-Checking Circuits' Operation 185
New High Speed CMOS Self-Checking Voter 184
Impact of ECCs on Simultaneously Switching Output Noise for On-Chip Busses of High Reliability Systems 184
10th IEEE International On-Line Testing Symposium 184
IEEE Transactions on Emerging Topics in Computing 184
Low-Cost Strategy for Bus Propagation Delay Reduction 184
Message from the Symposium Chairs 183
Reversible Gates and testability of One Dimensional Arrays of Molecular QCA 183
Novel Low-Cost Aging Sensor 182
Journal of Electronic Testing 181
Low-Cost and Highly Reliable Detector for Transient and Crosstalk Faults Affecting FPGA Interconnects 181
Novel On-Chip Clock Jitter Measurement Scheme For High Performance Microprocessors 180
Guest Editorial 179
Low Cost NBTI Degradation Detection and Masking Approaches 179
Configurable Error Control Scheme for NoC Signal Integrity 176
The 2019 IEEE Computer Society: Targeting Member Satisfaction and Technical Excellence 176
Novel High Speed Robust Latch 176
Low-Cost On-Chip Clock Jitter Measurement Scheme 175
On-Transistor Level Gate Sizing for Increased Robustness to Transient Faults 175
Faults Affecting the Control Blocks of PV Arrays and Techniques for Their Concurrent Detection 175
On the Reliability of Clock Monitoring Units for Safety Critical Applications’ Microcontrollers 174
The Other Side of the Timing Equation: a Result of Clock Faults 174
IEEE Transactions on Computers 174
Novel Compensation Scheme for Local Clocks of High Performance Microprocessors 173
Transient Fault and Soft Error On-Die Monitoring Scheme 173
Guest Editors' Introduction: Special Section on Concurrent On-Line Testing and Error/Fault Resilience of Digital Systems 173
Aging Resilient Ring Oscillators for Reliable Physically Unclonable Functions (PUFs) 170
Proceeding of 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems. 170
Low Cost Concurrent Error Detection Strategy for the Control Logic of High Performance Microprocessors and Its Application to the Instruction Decoder 170
A Novel Dual-Walled CNT Bus Architecture with Reduced Cross-Coupling Features 170
Special Section on Emerging Trends and Design Paradigms for Memory Systems and Storage 170
Modeling Crosstalk Effects in CNT Bus Architectures 170
Polynomial Based Key Distribution Scheme for WPAN 169
Proceedings 12th IEEE International On-Line Testing Symposium 168
Message from the Editor-in-Chief 168
12th IEEE International On-Line Testing Symposium 167
Power Consumption of Fault Tolerant Busses 167
Welcome Message 166
Welcome 166
New Design For Testability Approach for Clock Fault Testing 163
Coding Techniques for Low Switching Noise in Fault Tolerant Busses 162
Guest Editors' Introduction: Advances in VLSI Testing at MultiGbps Rates 161
Welcome 160
Totale 19.314
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Categoria #
all - tutte 65.601
article - articoli 0
book - libri 0
conference - conferenze 0
curatela - curatele 0
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 0
Totale 65.601
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2021/20225.857 0 53 830 718 768 615 633 637 689 164 326 424
2022/20232.057 259 284 99 291 147 161 97 128 306 25 166 94
2023/2024856 54 120 73 41 108 235 42 29 20 73 22 39
2024/20252.718 146 332 200 176 656 183 222 60 37 100 105 501
2025/20267.139 371 644 1.173 551 737 399 625 216 1.486 416 287 234
2026/2027462 188 274 0 0 0 0 0 0 0 0 0 0
Totale 26.120