CRIS Current Research Information System

METRA, CECILIA
 Distribuzione geografica
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Continente #
NA - Nord America 11.911
AS - Asia 6.863
EU - Europa 5.335
AF - Africa 358
SA - Sud America 302
OC - Oceania 8
Continente sconosciuto - Info sul continente non disponibili 5
Totale 24.782
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Nazione #
US - Stati Uniti d'America 11.848
CN - Cina 2.064
SG - Singapore 1.893
GB - Regno Unito 1.460
VN - Vietnam 1.338
IT - Italia 759
DE - Germania 707
UA - Ucraina 556
SE - Svezia 446
HK - Hong Kong 440
FR - Francia 413
IN - India 384
RU - Federazione Russa 308
BR - Brasile 207
JP - Giappone 198
KR - Corea 178
IE - Irlanda 162
ZA - Sudafrica 126
EE - Estonia 95
TG - Togo 90
BG - Bulgaria 85
FI - Finlandia 64
NL - Olanda 64
CI - Costa d'Avorio 61
TW - Taiwan 61
CH - Svizzera 52
PH - Filippine 48
SC - Seychelles 41
AR - Argentina 40
CA - Canada 40
TH - Thailandia 30
MY - Malesia 28
TR - Turchia 27
ID - Indonesia 26
PL - Polonia 25
BD - Bangladesh 24
IQ - Iraq 23
GR - Grecia 21
HR - Croazia 21
BE - Belgio 19
PK - Pakistan 17
MX - Messico 16
IR - Iran 15
AT - Austria 14
EC - Ecuador 14
SA - Arabia Saudita 13
CL - Cile 11
ES - Italia 11
PE - Perù 11
PT - Portogallo 10
DK - Danimarca 8
EG - Egitto 8
CO - Colombia 7
CZ - Repubblica Ceca 7
ET - Etiopia 7
LB - Libano 7
AU - Australia 6
DZ - Algeria 6
AE - Emirati Arabi Uniti 5
HU - Ungheria 5
IL - Israele 5
KE - Kenya 5
MA - Marocco 5
NO - Norvegia 5
UZ - Uzbekistan 5
AL - Albania 4
EU - Europa 4
PY - Paraguay 4
SI - Slovenia 4
AM - Armenia 3
CY - Cipro 3
GE - Georgia 3
JO - Giordania 3
KG - Kirghizistan 3
KP - Corea 3
KZ - Kazakistan 3
NP - Nepal 3
RO - Romania 3
TN - Tunisia 3
VE - Venezuela 3
BB - Barbados 2
BO - Bolivia 2
LA - Repubblica Popolare Democratica del Laos 2
NZ - Nuova Zelanda 2
OM - Oman 2
PA - Panama 2
PS - Palestinian Territory 2
RS - Serbia 2
SK - Slovacchia (Repubblica Slovacca) 2
SO - Somalia 2
UY - Uruguay 2
A2 - ???statistics.table.value.countryCode.A2??? 1
AZ - Azerbaigian 1
BY - Bielorussia 1
CM - Camerun 1
DO - Repubblica Dominicana 1
GA - Gabon 1
GF - Guiana Francese 1
GT - Guatemala 1
JM - Giamaica 1
Totale 24.775
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Città #
Ann Arbor 4.205
Singapore 1.300
Southend 1.224
Fairfield 800
Ashburn 689
Hefei 514
Wilmington 510
Chandler 505
Dallas 463
Santa Clara 421
Hong Kong 396
Woodbridge 389
Jacksonville 384
San Jose 373
Seattle 353
Ho Chi Minh City 305
Houston 302
Princeton 290
Cambridge 272
Hanoi 247
Beijing 244
Bologna 202
Boardman 182
Tokyo 176
Dong Ket 171
Dublin 160
Seoul 151
Lauterbourg 134
Westminster 129
Padova 126
Nanjing 125
Los Angeles 108
Berlin 98
Lomé 90
Medford 89
Sofia 84
Buffalo 82
Jinan 70
Mülheim 70
Milan 67
Shenyang 63
Saint Petersburg 62
Abidjan 60
Frankfurt am Main 50
Bengaluru 49
Helsinki 48
Da Nang 45
Hebei 44
San Diego 44
Guangzhou 43
Shanghai 43
Bern 41
Changsha 41
Washington 39
Tianjin 37
Mahé 35
Zhengzhou 33
Haiphong 31
Redondo Beach 30
Nanchang 27
New York 27
Des Moines 26
Munich 24
Chicago 21
São Paulo 21
Taipei 21
Verona 21
Yubileyny 21
Fremont 20
London 20
Paris 20
Rome 20
Council Bluffs 19
Taiyuan 19
Lanzhou 18
Norwalk 18
Amsterdam 16
Brussels 16
Hangzhou 16
Jiaxing 16
Olalla 16
Pune 16
Biên Hòa 15
Chennai 15
Qingdao 15
Toronto 15
Kunming 14
Montreal 14
Nuremberg 14
Taizhou 14
Bangkok 13
Fuzhou 13
Hải Dương 13
Warsaw 13
Costa Mesa 12
Dearborn 12
Delhi 12
Kuala Lumpur 12
Modena 12
Ningbo 12
Totale 18.037
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Nome #
IEEE Transactions on Emerging Topics in Computing 279
Low Cost and High Speed Embedded Two-Rail Code Checker 258
Self-Checking Voter for High Speed TMR Systems 236
Accurate Linear Model for SET Critical Charge Estimation 235
Model for Transient Fault Susceptibility of Combinational Circuits 234
On-Die Ring Oscillator Based Measurement Scheme for Process Parameter Variations and Clock Jitter 221
Clock Faults Induced Min and Max Delay Violations 217
New ECC for Crosstalk Effect Minimization 215
Fault-Tolerant Inverters for Reliable Photovoltaic Systems 215
Impact of Aging Phenomena on Latches’ Robustness 214
Concurrent Detection of Faults Affecting Energy Harvesting Circuits of Self-Powered Wearable Sensors 212
Faults Affecting Energy-Harvesting Circuits of Self-Powered Wireless Sensors and Their Possible Concurrent Detection 209
Implications of Clock Distribution Faults and Issues with Screening Them During Manufacturing Testing 208
Power droop reduction during Launch-On-Shift scan-based logic BIST 207
Low-Area On-Chip Circuit for Jitter Measurement in a Phase-Locked Loop 206
Testing Resistive Opens and Bridging Faults Through Pulse Propagation 204
Self-Checking Monitor for NBTI Due Degradation 204
High-Performance Robust Latches 203
AC/DC FAULT TOLERANT CODE 201
Early detection of photovoltaic system inverter faults 200
Exploiting ECC Redundancy to Minimize Crosstalk Impact 199
Are Our Design For Testability Features Fault Secure ? 199
Novel On-Chip Circuit for Jitter Testing in High-Speed PLLs 199
Modeling and Detection of Hotspot in Shaded Photovoltaic Cells 199
Multiple Transient Faults in Logic: An Issue for Next Generation ICs? 198
Won't On-Chip Clock Calibration Guarantee Performance Boost and Product Quality? 198
Low-Cost and High-Reduction Approaches for Power Droop during Launch-On-Shift Scan-Based Logic BIST 198
Checker No-Harm Alarms and Design Approaches to Tolerate Them 197
Low-Cost Strategy to Mitigate the Impact of Aging on Latches’ Robustness 197
Novel Physical Unclonable Function Implementation for Microcontrollers and Field Programmable Gate Arrays 195
Low Cost and Low Intrusive Approach to Test On-Line the Scheduler of High Performance Microprocessors 195
Intermittent and Transient Fault Diagnosis on Sparse Code Signatures 195
Impact of Aging Phenomena on Soft Error Susceptibility 195
Design & Test of Computers 194
Checker No-Harm Alarm Robustness 194
Hardware Reconfiguration Scheme for High Availability Systems 193
ACM Transactions on Design Automation of Electronic Systems 193
Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST 193
TMR voting in the presence of crosstalk faults at the voter inputs 193
Fast and Low-Cost Clock Deskew Buffer 191
Can Clock Faults Be Detected Through Functional Test ? 191
New Approaches for Power Binning of High Performance Microprocessors 191
Model for Thermal Behavior of Shaded Photovoltaic Cells Under Hot-Spot Condition 190
Error correcting code analysis for cache memory high reliability and performance 189
Novel Approach to Reduce Power Droop During Scan-Based Logic BIST 188
Proceedings 11th IEEE International On-Line Testing Symposium 186
Analysis of the Impact of Bus Implemented EDCs on On-Chip SSN 186
Impact of Bias Temperature Instability on Soft Error Susceptibility 186
On the Selection of Unidirectional Error detecting Codes for Self-Checking Circuits' Area Overhead and Performance Optimization 185
Fault secureness need for next generation high performance microprocessor design for testability structures 184
Should We Make Our Design for Testability Schemes Fault Secure ? 184
Function Inherent Code Checking: A New Low Cost On-Line Testing Approach for High Performance Microprocessor Control Logic 184
High-reliability Fault Tolerant Digital Systems in Nanometric Technologies: Characterization and Design Methodologies 184
Novel Approach to Clock Fault Testing for High Performance Microprocessors 183
Path (Min) delay Faults and Their Impact on Self-Checking Circuits' Operation 182
Load and Logic Co-Optimization for design of Soft-Error Resistant nanometer CMOS Circuits 181
New High Speed CMOS Self-Checking Voter 179
10th IEEE International On-Line Testing Symposium 179
Impact of ECCs on Simultaneously Switching Output Noise for On-Chip Busses of High Reliability Systems 178
Novel Low-Cost Aging Sensor 177
Low-Cost Strategy for Bus Propagation Delay Reduction 177
Novel On-Chip Clock Jitter Measurement Scheme For High Performance Microprocessors 177
Low Cost NBTI Degradation Detection and Masking Approaches 176
Message from the Symposium Chairs 175
Journal of Electronic Testing 174
IEEE Transactions on Emerging Topics in Computing 174
Guest Editorial 173
Low-Cost and Highly Reliable Detector for Transient and Crosstalk Faults Affecting FPGA Interconnects 173
Impact of aging on temperature measurements performed using a resistive temperature sensor with sensor-to-microcontroller direct interface 172
Low-Cost On-Chip Clock Jitter Measurement Scheme 172
On-Transistor Level Gate Sizing for Increased Robustness to Transient Faults 172
Novel High Speed Robust Latch 172
Faults Affecting the Control Blocks of PV Arrays and Techniques for Their Concurrent Detection 171
The 2019 IEEE Computer Society: Targeting Member Satisfaction and Technical Excellence 171
Reversible Gates and testability of One Dimensional Arrays of Molecular QCA 170
Transient Fault and Soft Error On-Die Monitoring Scheme 170
Guest Editors' Introduction: Special Section on Concurrent On-Line Testing and Error/Fault Resilience of Digital Systems 170
Silent Data Corruption and Reliability Risks due to Faults Affecting High Performance Microprocessors’ Caches 169
The Other Side of the Timing Equation: a Result of Clock Faults 169
Novel Compensation Scheme for Local Clocks of High Performance Microprocessors 169
On the Reliability of Clock Monitoring Units for Safety Critical Applications’ Microcontrollers 167
Low Cost Concurrent Error Detection Strategy for the Control Logic of High Performance Microprocessors and Its Application to the Instruction Decoder 167
A Novel Dual-Walled CNT Bus Architecture with Reduced Cross-Coupling Features 167
IEEE Transactions on Computers 167
Configurable Error Control Scheme for NoC Signal Integrity 166
Polynomial Based Key Distribution Scheme for WPAN 166
Special Section on Emerging Trends and Design Paradigms for Memory Systems and Storage 166
Proceeding of 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems. 165
Modeling Crosstalk Effects in CNT Bus Architectures 164
12th IEEE International On-Line Testing Symposium 163
Welcome 162
Message from the Editor-in-Chief 162
Aging Resilient Ring Oscillators for Reliable Physically Unclonable Functions (PUFs) 161
Power Consumption of Fault Tolerant Busses 161
Proceedings 12th IEEE International On-Line Testing Symposium 160
New Design For Testability Approach for Clock Fault Testing 160
Coding Techniques for Low Switching Noise in Fault Tolerant Busses 159
Guest Editors' Introduction: Advances in VLSI Testing at MultiGbps Rates 156
Simultaneous Switching Noise Analysis: The Relation Between Bus Layout and Coding 156
Latch Susceptibility to Transient Faults and New Hardening Approach 155
Totale 18.676
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Categoria #
all - tutte 59.372
article - articoli 0
book - libri 0
conference - conferenze 0
curatela - curatele 0
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 0
Totale 59.372
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2020/2021604 0 0 0 0 0 0 0 0 0 103 151 350
2021/20226.104 247 53 830 718 768 615 633 637 689 164 326 424
2022/20232.057 259 284 99 291 147 161 97 128 306 25 166 94
2023/2024856 54 120 73 41 108 235 42 29 20 73 22 39
2024/20252.718 146 332 200 176 656 183 222 60 37 100 105 501
2025/20266.528 371 644 1.173 551 737 399 625 216 1.486 326 0 0
Totale 25.047