CRIS Current Research Information System

METRA, CECILIA
 Distribuzione geografica
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Continente #
NA - Nord America 11.263
AS - Asia 5.101
EU - Europa 4.983
AF - Africa 331
SA - Sud America 258
OC - Oceania 8
Continente sconosciuto - Info sul continente non disponibili 5
Totale 21.949
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Nazione #
US - Stati Uniti d'America 11.221
CN - Cina 1.882
SG - Singapore 1.580
GB - Regno Unito 1.446
IT - Italia 679
DE - Germania 670
UA - Ucraina 553
SE - Svezia 444
VN - Vietnam 443
HK - Hong Kong 381
IN - India 345
RU - Federazione Russa 308
FR - Francia 264
BR - Brasile 176
KR - Corea 160
IE - Irlanda 158
JP - Giappone 136
ZA - Sudafrica 118
EE - Estonia 95
TG - Togo 90
BG - Bulgaria 85
CI - Costa d'Avorio 61
NL - Olanda 54
CH - Svizzera 50
SC - Seychelles 41
AR - Argentina 40
FI - Finlandia 36
TW - Taiwan 31
CA - Canada 29
MY - Malesia 24
ID - Indonesia 23
HR - Croazia 20
GR - Grecia 19
BE - Belgio 18
PL - Polonia 18
IR - Iran 15
AT - Austria 14
EC - Ecuador 12
PH - Filippine 10
BD - Bangladesh 9
CL - Cile 9
MX - Messico 9
PT - Portogallo 9
IQ - Iraq 8
PE - Perù 8
CZ - Repubblica Ceca 7
DK - Danimarca 7
TR - Turchia 7
AU - Australia 6
ES - Italia 6
LB - Libano 6
AE - Emirati Arabi Uniti 5
EG - Egitto 5
HU - Ungheria 5
NO - Norvegia 5
SA - Arabia Saudita 5
CO - Colombia 4
DZ - Algeria 4
EU - Europa 4
IL - Israele 4
MA - Marocco 4
PK - Pakistan 4
PY - Paraguay 4
SI - Slovenia 4
AL - Albania 3
AM - Armenia 3
ET - Etiopia 3
KE - Kenya 3
KP - Corea 3
TH - Thailandia 3
BB - Barbados 2
BO - Bolivia 2
CY - Cipro 2
JO - Giordania 2
KG - Kirghizistan 2
LA - Repubblica Popolare Democratica del Laos 2
NZ - Nuova Zelanda 2
RO - Romania 2
RS - Serbia 2
TN - Tunisia 2
UY - Uruguay 2
UZ - Uzbekistan 2
A2 - ???statistics.table.value.countryCode.A2??? 1
AZ - Azerbaigian 1
DO - Repubblica Dominicana 1
GE - Georgia 1
KW - Kuwait 1
LT - Lituania 1
MO - Macao, regione amministrativa speciale della Cina 1
PA - Panama 1
SK - Slovacchia (Repubblica Slovacca) 1
VE - Venezuela 1
Totale 21.949
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Città #
Ann Arbor 4.205
Southend 1.224
Singapore 1.018
Fairfield 800
Ashburn 601
Hefei 514
Wilmington 510
Chandler 505
Dallas 462
Santa Clara 415
Woodbridge 389
Jacksonville 384
Hong Kong 360
Seattle 353
Houston 301
Princeton 290
Cambridge 272
Beijing 235
Boardman 181
Dong Ket 171
Bologna 169
Dublin 156
Seoul 150
Westminster 129
Tokyo 127
Padova 126
Nanjing 125
Los Angeles 100
Berlin 98
Lomé 90
Medford 89
Sofia 84
Buffalo 80
Mülheim 70
Ho Chi Minh City 66
Jinan 66
Milan 64
Saint Petersburg 62
Shenyang 62
Abidjan 60
Bengaluru 49
Hebei 44
Hanoi 43
San Diego 43
Bern 41
Changsha 41
Washington 39
Tianjin 37
Mahé 35
Shanghai 35
Guangzhou 31
Zhengzhou 31
Redondo Beach 30
Nanchang 27
Frankfurt am Main 25
Des Moines 24
Munich 23
Helsinki 21
Yubileyny 21
Chicago 20
Fremont 20
Verona 20
Lanzhou 18
Norwalk 18
Taiyuan 18
São Paulo 17
Jiaxing 16
New York 16
Olalla 16
Pune 16
Rome 16
Brussels 15
London 15
Kunming 14
Qingdao 14
Taizhou 14
Hangzhou 13
Paris 13
Taipei 13
Toronto 13
Costa Mesa 12
Dearborn 12
Delhi 12
Fuzhou 12
Ningbo 12
Nuremberg 12
Amsterdam 11
Kuala Lumpur 11
Modena 11
Turin 11
Chennai 10
Phoenix 10
Redwood City 10
Turku 10
Biên Hòa 9
Chongqing 9
Montreal 9
Moscow 9
San Venanzo 9
Vienna 9
Totale 16.348
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Nome #
IEEE Transactions on Emerging Topics in Computing 245
Low Cost and High Speed Embedded Two-Rail Code Checker 237
Self-Checking Voter for High Speed TMR Systems 224
Model for Transient Fault Susceptibility of Combinational Circuits 224
Accurate Linear Model for SET Critical Charge Estimation 214
New ECC for Crosstalk Effect Minimization 203
On-Die Ring Oscillator Based Measurement Scheme for Process Parameter Variations and Clock Jitter 200
Self-Checking Monitor for NBTI Due Degradation 199
Concurrent Detection of Faults Affecting Energy Harvesting Circuits of Self-Powered Wearable Sensors 196
Clock Faults Induced Min and Max Delay Violations 195
Implications of Clock Distribution Faults and Issues with Screening Them During Manufacturing Testing 192
Exploiting ECC Redundancy to Minimize Crosstalk Impact 190
Are Our Design For Testability Features Fault Secure ? 189
Multiple Transient Faults in Logic: An Issue for Next Generation ICs? 187
Fault-Tolerant Inverters for Reliable Photovoltaic Systems 187
Checker No-Harm Alarm Robustness 186
Checker No-Harm Alarms and Design Approaches to Tolerate Them 186
Testing Resistive Opens and Bridging Faults Through Pulse Propagation 186
High-Performance Robust Latches 186
Hardware Reconfiguration Scheme for High Availability Systems 185
Low-Area On-Chip Circuit for Jitter Measurement in a Phase-Locked Loop 183
Can Clock Faults Be Detected Through Functional Test ? 183
Novel On-Chip Circuit for Jitter Testing in High-Speed PLLs 183
AC/DC FAULT TOLERANT CODE 181
Impact of Aging Phenomena on Latches’ Robustness 181
Low-Cost and High-Reduction Approaches for Power Droop during Launch-On-Shift Scan-Based Logic BIST 181
Fast and Low-Cost Clock Deskew Buffer 180
Low Cost and Low Intrusive Approach to Test On-Line the Scheduler of High Performance Microprocessors 180
Impact of Aging Phenomena on Soft Error Susceptibility 180
New Approaches for Power Binning of High Performance Microprocessors 179
Analysis of the Impact of Bus Implemented EDCs on On-Chip SSN 178
Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST 178
Faults Affecting Energy-Harvesting Circuits of Self-Powered Wireless Sensors and Their Possible Concurrent Detection 177
Intermittent and Transient Fault Diagnosis on Sparse Code Signatures 177
TMR voting in the presence of crosstalk faults at the voter inputs 177
On the Selection of Unidirectional Error detecting Codes for Self-Checking Circuits' Area Overhead and Performance Optimization 174
Fault secureness need for next generation high performance microprocessor design for testability structures 174
Won't On-Chip Clock Calibration Guarantee Performance Boost and Product Quality? 174
Early detection of photovoltaic system inverter faults 173
Power droop reduction during Launch-On-Shift scan-based logic BIST 173
Path (Min) delay Faults and Their Impact on Self-Checking Circuits' Operation 172
Design & Test of Computers 171
Low-Cost Strategy to Mitigate the Impact of Aging on Latches’ Robustness 171
Load and Logic Co-Optimization for design of Soft-Error Resistant nanometer CMOS Circuits 170
Model for Thermal Behavior of Shaded Photovoltaic Cells Under Hot-Spot Condition 170
Novel Approach to Clock Fault Testing for High Performance Microprocessors 169
ACM Transactions on Design Automation of Electronic Systems 168
New High Speed CMOS Self-Checking Voter 167
Proceedings 11th IEEE International On-Line Testing Symposium 167
Error correcting code analysis for cache memory high reliability and performance 167
Impact of ECCs on Simultaneously Switching Output Noise for On-Chip Busses of High Reliability Systems 166
Novel Approach to Reduce Power Droop During Scan-Based Logic BIST 166
Should We Make Our Design for Testability Schemes Fault Secure ? 165
Message from the Symposium Chairs 164
10th IEEE International On-Line Testing Symposium 163
High-reliability Fault Tolerant Digital Systems in Nanometric Technologies: Characterization and Design Methodologies 163
Novel High Speed Robust Latch 163
Low-Cost and Highly Reliable Detector for Transient and Crosstalk Faults Affecting FPGA Interconnects 162
Function Inherent Code Checking: A New Low Cost On-Line Testing Approach for High Performance Microprocessor Control Logic 162
Transient Fault and Soft Error On-Die Monitoring Scheme 162
Impact of Bias Temperature Instability on Soft Error Susceptibility 161
Low Cost NBTI Degradation Detection and Masking Approaches 161
Modeling and Detection of Hotspot in Shaded Photovoltaic Cells 160
The Other Side of the Timing Equation: a Result of Clock Faults 159
Journal of Electronic Testing 159
Reversible Gates and testability of One Dimensional Arrays of Molecular QCA 159
On-Transistor Level Gate Sizing for Increased Robustness to Transient Faults 159
Novel Low-Cost Aging Sensor 159
Guest Editorial 157
Low-Cost Strategy for Bus Propagation Delay Reduction 157
Novel Compensation Scheme for Local Clocks of High Performance Microprocessors 155
A Novel Dual-Walled CNT Bus Architecture with Reduced Cross-Coupling Features 155
Configurable Error Control Scheme for NoC Signal Integrity 154
Faults Affecting the Control Blocks of PV Arrays and Techniques for Their Concurrent Detection 154
The 2019 IEEE Computer Society: Targeting Member Satisfaction and Technical Excellence 154
IEEE Transactions on Emerging Topics in Computing 153
Low-Cost On-Chip Clock Jitter Measurement Scheme 152
Guest Editors' Introduction: Special Section on Concurrent On-Line Testing and Error/Fault Resilience of Digital Systems 152
Modeling Crosstalk Effects in CNT Bus Architectures 152
Welcome 151
Low Cost Concurrent Error Detection Strategy for the Control Logic of High Performance Microprocessors and Its Application to the Instruction Decoder 151
Novel Physical Unclonable Function Implementation for Microcontrollers and Field Programmable Gate Arrays 150
Power Consumption of Fault Tolerant Busses 150
Proceeding of 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems. 149
Guest Editors' Introduction: Advances in VLSI Testing at MultiGbps Rates 149
New Design For Testability Approach for Clock Fault Testing 148
Novel On-Chip Clock Jitter Measurement Scheme For High Performance Microprocessors 148
Special Section on Emerging Trends and Design Paradigms for Memory Systems and Storage 148
Message from the Editor-in-Chief 147
Proceedings 12th IEEE International On-Line Testing Symposium 146
12th IEEE International On-Line Testing Symposium 145
IEEE Transactions on Computers 145
Coding Techniques for Low Switching Noise in Fault Tolerant Busses 145
Risks Associated with Faults within Test Pattern Compactors and Their Implications on Testing 144
Latch Susceptibility to Transient Faults and New Hardening Approach 143
Simultaneous Switching Noise Analysis: The Relation Between Bus Layout and Coding 141
Low-Cost Dynamic Compensation Scheme for Local Clocks of Next Generation High Performance Microprocessors 140
Guest Editors' Introduction: The State of the Art in Nanoscale CAD 139
Welcome 138
11th IEEE International On-Line Testing Symposium 138
Totale 16.932
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Categoria #
all - tutte 54.265
article - articoli 0
book - libri 0
conference - conferenze 0
curatela - curatele 0
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 0
Totale 54.265
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2020/20211.155 0 0 0 0 0 217 23 136 175 103 151 350
2021/20226.104 247 53 830 718 768 615 633 637 689 164 326 424
2022/20232.057 259 284 99 291 147 161 97 128 306 25 166 94
2023/2024856 54 120 73 41 108 235 42 29 20 73 22 39
2024/20252.718 146 332 200 176 656 183 222 60 37 100 105 501
2025/20263.678 371 644 1.173 551 737 202 0 0 0 0 0 0
Totale 22.197