CRIS Current Research Information System

METRA, CECILIA
 Distribuzione geografica
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Continente #
NA - Nord America 10.100
EU - Europa 4.462
AS - Asia 1.987
AF - Africa 250
SA - Sud America 17
Continente sconosciuto - Info sul continente non disponibili 5
OC - Oceania 5
Totale 16.826
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Nazione #
US - Stati Uniti d'America 10.087
GB - Regno Unito 1.422
CN - Cina 791
DE - Germania 599
UA - Ucraina 550
IT - Italia 540
SG - Singapore 495
SE - Svezia 439
VN - Vietnam 275
IN - India 271
FR - Francia 220
RU - Federazione Russa 181
IE - Irlanda 150
ZA - Sudafrica 111
EE - Estonia 95
TG - Togo 90
BG - Bulgaria 85
CH - Svizzera 48
SC - Seychelles 37
JP - Giappone 36
HR - Croazia 20
TW - Taiwan 20
GR - Grecia 19
MY - Malesia 18
BE - Belgio 15
IR - Iran 15
HK - Hong Kong 14
ID - Indonesia 13
NL - Olanda 13
FI - Finlandia 12
BR - Brasile 11
CA - Canada 10
PT - Portogallo 9
KR - Corea 8
PL - Polonia 8
DK - Danimarca 7
AT - Austria 6
LB - Libano 6
CZ - Repubblica Ceca 5
CI - Costa d'Avorio 4
ES - Italia 4
EU - Europa 4
NO - Norvegia 4
SI - Slovenia 4
AU - Australia 3
CL - Cile 3
DZ - Algeria 3
IL - Israele 3
IQ - Iraq 3
KP - Corea 3
MX - Messico 3
PK - Pakistan 3
TR - Turchia 3
AL - Albania 2
AR - Argentina 2
EG - Egitto 2
ET - Etiopia 2
LA - Repubblica Popolare Democratica del Laos 2
NZ - Nuova Zelanda 2
RO - Romania 2
RS - Serbia 2
A2 - ???statistics.table.value.countryCode.A2??? 1
AM - Armenia 1
AZ - Azerbaigian 1
BD - Bangladesh 1
BO - Bolivia 1
KG - Kirghizistan 1
KW - Kuwait 1
MA - Marocco 1
MO - Macao, regione amministrativa speciale della Cina 1
PH - Filippine 1
SA - Arabia Saudita 1
SK - Slovacchia (Repubblica Slovacca) 1
Totale 16.826
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Città #
Ann Arbor 4.205
Southend 1.224
Fairfield 800
Wilmington 509
Ashburn 507
Chandler 505
Singapore 429
Woodbridge 389
Jacksonville 384
Seattle 353
Houston 301
Princeton 290
Cambridge 272
Boardman 180
Santa Clara 175
Dong Ket 171
Dublin 148
Westminster 129
Padova 126
Nanjing 125
Bologna 123
Berlin 98
Lomé 90
Medford 89
Sofia 84
Mülheim 70
Jinan 64
Saint Petersburg 62
Shenyang 59
Beijing 56
Milan 45
Hebei 44
San Diego 43
Bern 41
Washington 39
Changsha 35
Mahé 35
Tianjin 34
Los Angeles 33
Tokyo 33
Nanchang 27
Zhengzhou 27
Des Moines 23
Fremont 20
Guangzhou 20
Shanghai 20
Verona 20
Lanzhou 18
Norwalk 18
Taiyuan 18
Olalla 16
Pune 16
Jiaxing 15
Brussels 14
Taizhou 14
Hangzhou 13
Kunming 13
Costa Mesa 12
Dearborn 12
Ningbo 12
Paris 12
Fuzhou 11
Delhi 10
Helsinki 10
Modena 10
Redwood City 10
San Venanzo 9
Bühl 8
Haikou 8
Taipei 8
Turin 8
Falls Church 7
London 7
Shenzhen 7
São Paulo 7
Amsterdam 6
Chongqing 6
Dallas 6
Jakarta 6
New York 6
San Jose 6
Toronto 6
Canosa Di Puglia 5
Chennai 5
Kuala Lumpur 5
Malacca 5
New Taipei 5
Portomaggiore 5
Qingdao 5
Suzhou 5
Vienna 5
Villanova d'Albenga 5
Xi'an 5
Abidjan 4
Chicago 4
Frankfurt Am Main 4
Frankfurt am Main 4
Hefei 4
Hyderabad 4
Muizenberg 4
Totale 13.004
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Nome #
Accurate Linear Model for SET Critical Charge Estimation 189
Low Cost and High Speed Embedded Two-Rail Code Checker 182
Self-Checking Voter for High Speed TMR Systems 179
Model for Transient Fault Susceptibility of Combinational Circuits 178
Concurrent Detection of Faults Affecting Energy Harvesting Circuits of Self-Powered Wearable Sensors 173
Clock Faults Induced Min and Max Delay Violations 170
Self-Checking Monitor for NBTI Due Degradation 169
On-Die Ring Oscillator Based Measurement Scheme for Process Parameter Variations and Clock Jitter 165
Checker No-Harm Alarms and Design Approaches to Tolerate Them 160
Testing Resistive Opens and Bridging Faults Through Pulse Propagation 160
New ECC for Crosstalk Effect Minimization 159
High-Performance Robust Latches 158
TMR voting in the presence of crosstalk faults at the voter inputs 156
Novel On-Chip Circuit for Jitter Testing in High-Speed PLLs 155
Low-Cost and High-Reduction Approaches for Power Droop during Launch-On-Shift Scan-Based Logic BIST 154
Implications of Clock Distribution Faults and Issues with Screening Them During Manufacturing Testing 153
Checker No-Harm Alarm Robustness 153
Low Cost and Low Intrusive Approach to Test On-Line the Scheduler of High Performance Microprocessors 153
Impact of Aging Phenomena on Latches’ Robustness 152
Can Clock Faults Be Detected Through Functional Test ? 151
Intermittent and Transient Fault Diagnosis on Sparse Code Signatures 151
Impact of Aging Phenomena on Soft Error Susceptibility 151
Exploiting ECC Redundancy to Minimize Crosstalk Impact 150
Multiple Transient Faults in Logic: An Issue for Next Generation ICs? 150
Are Our Design For Testability Features Fault Secure ? 150
Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST 149
New Approaches for Power Binning of High Performance Microprocessors 149
Fault-Tolerant Inverters for Reliable Photovoltaic Systems 149
Faults Affecting Energy-Harvesting Circuits of Self-Powered Wireless Sensors and Their Possible Concurrent Detection 148
Power droop reduction during Launch-On-Shift scan-based logic BIST 148
Novel Approach to Clock Fault Testing for High Performance Microprocessors 146
Low-Cost Strategy to Mitigate the Impact of Aging on Latches’ Robustness 146
Hardware Reconfiguration Scheme for High Availability Systems 144
Analysis of the Impact of Bus Implemented EDCs on On-Chip SSN 144
AC/DC FAULT TOLERANT CODE 142
Novel Approach to Reduce Power Droop During Scan-Based Logic BIST 141
Novel High Speed Robust Latch 141
Fast and Low-Cost Clock Deskew Buffer 140
Error correcting code analysis for cache memory high reliability and performance 140
Low-Area On-Chip Circuit for Jitter Measurement in a Phase-Locked Loop 139
Path (Min) delay Faults and Their Impact on Self-Checking Circuits' Operation 139
On-Transistor Level Gate Sizing for Increased Robustness to Transient Faults 139
On the Selection of Unidirectional Error detecting Codes for Self-Checking Circuits' Area Overhead and Performance Optimization 138
Fault secureness need for next generation high performance microprocessor design for testability structures 138
Model for Thermal Behavior of Shaded Photovoltaic Cells Under Hot-Spot Condition 138
Impact of Bias Temperature Instability on Soft Error Susceptibility 138
IEEE Transactions on Emerging Topics in Computing 138
Transient Fault and Soft Error On-Die Monitoring Scheme 137
Novel Compensation Scheme for Local Clocks of High Performance Microprocessors 136
Function Inherent Code Checking: A New Low Cost On-Line Testing Approach for High Performance Microprocessor Control Logic 136
High-reliability Fault Tolerant Digital Systems in Nanometric Technologies: Characterization and Design Methodologies 136
Won't On-Chip Clock Calibration Guarantee Performance Boost and Product Quality? 135
A Novel Dual-Walled CNT Bus Architecture with Reduced Cross-Coupling Features 134
Faults Affecting the Control Blocks of PV Arrays and Techniques for Their Concurrent Detection 134
Design & Test of Computers 133
Reversible Gates and testability of One Dimensional Arrays of Molecular QCA 133
Configurable Error Control Scheme for NoC Signal Integrity 133
Power Consumption of Fault Tolerant Busses 133
Low Cost Concurrent Error Detection Strategy for the Control Logic of High Performance Microprocessors and Its Application to the Instruction Decoder 133
Modeling and Detection of Hotspot in Shaded Photovoltaic Cells 133
New Design For Testability Approach for Clock Fault Testing 132
Novel Low-Cost Aging Sensor 132
Novel On-Chip Clock Jitter Measurement Scheme For High Performance Microprocessors 132
The 2019 IEEE Computer Society: Targeting Member Satisfaction and Technical Excellence 132
Load and Logic Co-Optimization for design of Soft-Error Resistant nanometer CMOS Circuits 131
Low Cost NBTI Degradation Detection and Masking Approaches 131
Coding Techniques for Low Switching Noise in Fault Tolerant Busses 131
Modeling Crosstalk Effects in CNT Bus Architectures 131
Guest Editors' Introduction: Special Section on Concurrent On-Line Testing and Error/Fault Resilience of Digital Systems 130
Guest Editors' Introduction: Advances in VLSI Testing at MultiGbps Rates 129
Proceedings 11th IEEE International On-Line Testing Symposium 127
Low-Cost On-Chip Clock Jitter Measurement Scheme 127
Low-Cost Strategy for Bus Propagation Delay Reduction 127
Risks Associated with Faults within Test Pattern Compactors and Their Implications on Testing 127
Special Section on Emerging Trends and Design Paradigms for Memory Systems and Storage 127
New High Speed CMOS Self-Checking Voter 126
Should We Make Our Design for Testability Schemes Fault Secure ? 126
Low-Cost and Highly Reliable Detector for Transient and Crosstalk Faults Affecting FPGA Interconnects 126
Latch Susceptibility to Transient Faults and New Hardening Approach 126
10th IEEE International On-Line Testing Symposium 125
Simultaneous Switching Noise Analysis: The Relation Between Bus Layout and Coding 125
The Other Side of the Timing Equation: a Result of Clock Faults 123
Message from the Editor-in-Chief 123
Message from the Symposium Chairs 122
Welcome 122
Impact of ECCs on Simultaneously Switching Output Noise for On-Chip Busses of High Reliability Systems 121
Low-Cost Dynamic Compensation Scheme for Local Clocks of Next Generation High Performance Microprocessors 121
Guest Editorial 120
Risks for Signal Integrity in System in Package and Possible Remedies 120
Guest Editors' Introduction: The State of the Art in Nanoscale CAD 120
12th IEEE International On-Line Testing Symposium 118
Proceedings 12th IEEE International On-Line Testing Symposium 117
Journal of Electronic Testing 116
Polynomial Based Key Distribution Scheme for WPAN 116
Polynomial Based Key Distribution Scheme for WPAN 116
Proceeding of 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems. 113
Inverters' Self-Checking Monitors for Reliable Photovoltaic Systems 112
Welcome Message from the Chairs 110
ACM Transactions on Design Automation of Electronic Systems 110
Proceedings 10th IEEE International On-Line Testing Symposium 110
Totale 13.831
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Categoria #
all - tutte 38.082
article - articoli 0
book - libri 0
conference - conferenze 0
curatela - curatele 0
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 0
Totale 38.082
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2019/20202.538 0 0 0 0 325 340 409 522 447 234 101 160
2020/20211.987 504 162 53 87 26 217 23 136 175 103 151 350
2021/20226.104 247 53 830 718 768 615 633 637 689 164 326 424
2022/20232.057 259 284 99 291 147 161 97 128 306 25 166 94
2023/2024856 54 120 73 41 108 235 42 29 20 73 22 39
2024/20251.235 146 332 200 176 381 0 0 0 0 0 0 0
Totale 17.036