CRIS Current Research Information System

METRA, CECILIA
 Distribuzione geografica
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Continente #
NA - Nord America 12.349
AS - Asia 6.926
EU - Europa 5.419
AF - Africa 359
SA - Sud America 304
OC - Oceania 10
Continente sconosciuto - Info sul continente non disponibili 5
Totale 25.372
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Nazione #
US - Stati Uniti d'America 12.264
CN - Cina 2.072
SG - Singapore 1.901
GB - Regno Unito 1.465
VN - Vietnam 1.339
IT - Italia 832
DE - Germania 708
UA - Ucraina 556
HK - Hong Kong 447
SE - Svezia 446
FR - Francia 413
IN - India 384
RU - Federazione Russa 308
BR - Brasile 209
JP - Giappone 199
KR - Corea 179
IE - Irlanda 162
ZA - Sudafrica 126
EE - Estonia 95
TG - Togo 90
BG - Bulgaria 85
NL - Olanda 67
FI - Finlandia 64
TW - Taiwan 62
CI - Costa d'Avorio 61
BD - Bangladesh 58
CA - Canada 52
CH - Svizzera 52
PH - Filippine 48
SC - Seychelles 41
AR - Argentina 40
TH - Thailandia 30
MY - Malesia 28
ID - Indonesia 27
TR - Turchia 27
PL - Polonia 25
IQ - Iraq 23
MX - Messico 23
GR - Grecia 21
HR - Croazia 21
BE - Belgio 19
PK - Pakistan 17
IR - Iran 15
AT - Austria 14
EC - Ecuador 14
SA - Arabia Saudita 13
CL - Cile 11
ES - Italia 11
PE - Perù 11
PT - Portogallo 10
EG - Egitto 9
AU - Australia 8
DK - Danimarca 8
CO - Colombia 7
CZ - Repubblica Ceca 7
ET - Etiopia 7
LB - Libano 7
DZ - Algeria 6
AE - Emirati Arabi Uniti 5
HU - Ungheria 5
IL - Israele 5
KE - Kenya 5
MA - Marocco 5
NO - Norvegia 5
UZ - Uzbekistan 5
AL - Albania 4
EU - Europa 4
GE - Georgia 4
PY - Paraguay 4
SI - Slovenia 4
AM - Armenia 3
CY - Cipro 3
JO - Giordania 3
KG - Kirghizistan 3
KP - Corea 3
KZ - Kazakistan 3
NP - Nepal 3
RO - Romania 3
TN - Tunisia 3
VE - Venezuela 3
BB - Barbados 2
BO - Bolivia 2
LA - Repubblica Popolare Democratica del Laos 2
MD - Moldavia 2
NZ - Nuova Zelanda 2
OM - Oman 2
PA - Panama 2
PS - Palestinian Territory 2
RS - Serbia 2
SK - Slovacchia (Repubblica Slovacca) 2
SO - Somalia 2
UY - Uruguay 2
A2 - ???statistics.table.value.countryCode.A2??? 1
AW - Aruba 1
AZ - Azerbaigian 1
BY - Bielorussia 1
CM - Camerun 1
DO - Repubblica Dominicana 1
GA - Gabon 1
GF - Guiana Francese 1
Totale 25.361
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Città #
Ann Arbor 4.205
Singapore 1.305
Southend 1.224
Fairfield 800
Ashburn 723
Hefei 514
Wilmington 510
Chandler 505
Dallas 473
San Jose 441
Santa Clara 434
Hong Kong 403
Woodbridge 389
Jacksonville 385
Seattle 353
Ho Chi Minh City 305
Houston 302
Princeton 290
Cambridge 272
Beijing 248
Hanoi 248
Bologna 219
Boardman 192
Tokyo 176
Dong Ket 171
Dublin 160
Seoul 151
Lauterbourg 134
Westminster 129
Los Angeles 126
Padova 126
Nanjing 125
Council Bluffs 121
Berlin 98
Lomé 90
Medford 89
Sofia 84
Milan 83
Buffalo 82
Jinan 70
Mülheim 70
Shenyang 63
Saint Petersburg 62
Abidjan 60
New York 51
Frankfurt am Main 50
Bengaluru 49
Helsinki 48
Da Nang 45
Hebei 44
San Diego 44
Guangzhou 43
Shanghai 43
Bern 41
Changsha 41
Washington 40
Tianjin 37
Mahé 35
Zhengzhou 33
Haiphong 31
Redondo Beach 30
Chicago 28
Des Moines 27
Nanchang 27
Rome 25
Munich 24
São Paulo 22
London 21
Taipei 21
Verona 21
Yubileyny 21
Fremont 20
Paris 20
San Francisco 19
Taiyuan 19
Lanzhou 18
Montreal 18
Norwalk 18
Toronto 18
Amsterdam 16
Brussels 16
Hangzhou 16
Jiaxing 16
Olalla 16
Phoenix 16
Pune 16
Biên Hòa 15
Chennai 15
Qingdao 15
Kunming 14
Nuremberg 14
Taizhou 14
Atlanta 13
Bangkok 13
Fuzhou 13
Hải Dương 13
Warsaw 13
Brooklyn 12
Costa Mesa 12
Dearborn 12
Totale 18.402
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Nome #
IEEE Transactions on Emerging Topics in Computing 292
Low Cost and High Speed Embedded Two-Rail Code Checker 259
Model for Transient Fault Susceptibility of Combinational Circuits 237
Self-Checking Voter for High Speed TMR Systems 236
Accurate Linear Model for SET Critical Charge Estimation 236
On-Die Ring Oscillator Based Measurement Scheme for Process Parameter Variations and Clock Jitter 223
Novel Physical Unclonable Function Implementation for Microcontrollers and Field Programmable Gate Arrays 219
Clock Faults Induced Min and Max Delay Violations 218
New ECC for Crosstalk Effect Minimization 217
Low-Area On-Chip Circuit for Jitter Measurement in a Phase-Locked Loop 216
Impact of Aging Phenomena on Latches’ Robustness 216
Fault-Tolerant Inverters for Reliable Photovoltaic Systems 215
Concurrent Detection of Faults Affecting Energy Harvesting Circuits of Self-Powered Wearable Sensors 214
Faults Affecting Energy-Harvesting Circuits of Self-Powered Wireless Sensors and Their Possible Concurrent Detection 214
High-Performance Robust Latches 213
Implications of Clock Distribution Faults and Issues with Screening Them During Manufacturing Testing 209
Testing Resistive Opens and Bridging Faults Through Pulse Propagation 209
Early detection of photovoltaic system inverter faults 207
Won't On-Chip Clock Calibration Guarantee Performance Boost and Product Quality? 207
Power droop reduction during Launch-On-Shift scan-based logic BIST 207
AC/DC FAULT TOLERANT CODE 206
Self-Checking Monitor for NBTI Due Degradation 205
Are Our Design For Testability Features Fault Secure ? 203
Novel On-Chip Circuit for Jitter Testing in High-Speed PLLs 203
Modeling and Detection of Hotspot in Shaded Photovoltaic Cells 203
Exploiting ECC Redundancy to Minimize Crosstalk Impact 200
Multiple Transient Faults in Logic: An Issue for Next Generation ICs? 199
Design & Test of Computers 199
Checker No-Harm Alarms and Design Approaches to Tolerate Them 199
Low-Cost Strategy to Mitigate the Impact of Aging on Latches’ Robustness 199
Low-Cost and High-Reduction Approaches for Power Droop during Launch-On-Shift Scan-Based Logic BIST 199
Hardware Reconfiguration Scheme for High Availability Systems 198
Checker No-Harm Alarm Robustness 197
ACM Transactions on Design Automation of Electronic Systems 196
Low Cost and Low Intrusive Approach to Test On-Line the Scheduler of High Performance Microprocessors 195
Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST 195
Intermittent and Transient Fault Diagnosis on Sparse Code Signatures 195
TMR voting in the presence of crosstalk faults at the voter inputs 195
Impact of Aging Phenomena on Soft Error Susceptibility 195
Fast and Low-Cost Clock Deskew Buffer 194
Can Clock Faults Be Detected Through Functional Test ? 194
Error correcting code analysis for cache memory high reliability and performance 194
New Approaches for Power Binning of High Performance Microprocessors 193
Proceedings 11th IEEE International On-Line Testing Symposium 191
Model for Thermal Behavior of Shaded Photovoltaic Cells Under Hot-Spot Condition 191
Impact of Bias Temperature Instability on Soft Error Susceptibility 191
Novel Approach to Reduce Power Droop During Scan-Based Logic BIST 190
Should We Make Our Design for Testability Schemes Fault Secure ? 189
Analysis of the Impact of Bus Implemented EDCs on On-Chip SSN 189
On the Selection of Unidirectional Error detecting Codes for Self-Checking Circuits' Area Overhead and Performance Optimization 188
Function Inherent Code Checking: A New Low Cost On-Line Testing Approach for High Performance Microprocessor Control Logic 187
Fault secureness need for next generation high performance microprocessor design for testability structures 186
Novel Approach to Clock Fault Testing for High Performance Microprocessors 185
Load and Logic Co-Optimization for design of Soft-Error Resistant nanometer CMOS Circuits 184
Path (Min) delay Faults and Their Impact on Self-Checking Circuits' Operation 184
High-reliability Fault Tolerant Digital Systems in Nanometric Technologies: Characterization and Design Methodologies 184
New High Speed CMOS Self-Checking Voter 183
Silent Data Corruption and Reliability Risks due to Faults Affecting High Performance Microprocessors’ Caches 182
10th IEEE International On-Line Testing Symposium 182
Message from the Symposium Chairs 182
Impact of ECCs on Simultaneously Switching Output Noise for On-Chip Busses of High Reliability Systems 180
IEEE Transactions on Emerging Topics in Computing 180
Low-Cost Strategy for Bus Propagation Delay Reduction 180
Guest Editorial 178
Journal of Electronic Testing 178
Novel Low-Cost Aging Sensor 178
Low Cost NBTI Degradation Detection and Masking Approaches 178
Impact of aging on temperature measurements performed using a resistive temperature sensor with sensor-to-microcontroller direct interface 177
Novel On-Chip Clock Jitter Measurement Scheme For High Performance Microprocessors 177
Low-Cost and Highly Reliable Detector for Transient and Crosstalk Faults Affecting FPGA Interconnects 176
Reversible Gates and testability of One Dimensional Arrays of Molecular QCA 176
Configurable Error Control Scheme for NoC Signal Integrity 174
On the Reliability of Clock Monitoring Units for Safety Critical Applications’ Microcontrollers 173
Low-Cost On-Chip Clock Jitter Measurement Scheme 173
On-Transistor Level Gate Sizing for Increased Robustness to Transient Faults 173
Faults Affecting the Control Blocks of PV Arrays and Techniques for Their Concurrent Detection 173
The 2019 IEEE Computer Society: Targeting Member Satisfaction and Technical Excellence 173
Novel High Speed Robust Latch 173
The Other Side of the Timing Equation: a Result of Clock Faults 172
Novel Compensation Scheme for Local Clocks of High Performance Microprocessors 172
Transient Fault and Soft Error On-Die Monitoring Scheme 172
IEEE Transactions on Computers 171
Guest Editors' Introduction: Special Section on Concurrent On-Line Testing and Error/Fault Resilience of Digital Systems 170
Proceeding of 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems. 169
Special Section on Emerging Trends and Design Paradigms for Memory Systems and Storage 169
Aging Resilient Ring Oscillators for Reliable Physically Unclonable Functions (PUFs) 168
Low Cost Concurrent Error Detection Strategy for the Control Logic of High Performance Microprocessors and Its Application to the Instruction Decoder 168
A Novel Dual-Walled CNT Bus Architecture with Reduced Cross-Coupling Features 168
12th IEEE International On-Line Testing Symposium 166
Polynomial Based Key Distribution Scheme for WPAN 166
Message from the Editor-in-Chief 166
Power Consumption of Fault Tolerant Busses 165
Modeling Crosstalk Effects in CNT Bus Architectures 165
Welcome 164
Proceedings 12th IEEE International On-Line Testing Symposium 164
Welcome Message 161
New Design For Testability Approach for Clock Fault Testing 161
Coding Techniques for Low Switching Noise in Fault Tolerant Busses 161
Guest Editors' Introduction: Advances in VLSI Testing at MultiGbps Rates 159
Welcome 158
Totale 19.013
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Categoria #
all - tutte 63.033
article - articoli 0
book - libri 0
conference - conferenze 0
curatela - curatele 0
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 0
Totale 63.033
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2020/2021350 0 0 0 0 0 0 0 0 0 0 0 350
2021/20226.104 247 53 830 718 768 615 633 637 689 164 326 424
2022/20232.057 259 284 99 291 147 161 97 128 306 25 166 94
2023/2024856 54 120 73 41 108 235 42 29 20 73 22 39
2024/20252.718 146 332 200 176 656 183 222 60 37 100 105 501
2025/20267.120 371 644 1.173 551 737 399 625 216 1.486 416 287 215
Totale 25.639