In this paper, we analyze the effects of aging mechanisms on the soft error susceptibility of both standard and robust latches. Particularly, we consider bias temperature instability (BTI) affecting both nMOS (positive BTI) and pMOS (negative BTI), which is considered the most critical aging mechanism threatening the reliability of ICs. Our analyses show that as an IC ages, BTI significantly increases the susceptibility of both standard latches and low-cost robust latches, whose robustness is based on the increase in the critical charge of their most susceptible node(s). Instead, we will show that BTI minimally affects the soft error susceptibility of more costly robust latches that avoid the generation of soft errors by design. Consequently, our analysis highlights the fact that in applications mandating the use of low-cost robust latches, designers will have to face the problem of their robustness degradation during IC lifetime. Therefore, for these applications, designers will have to develop proper low-cost solutions to guarantee the minimal required level of robustness during the whole IC lifetime.

Impact of Aging Phenomena on Latches’ Robustness

OMANA, MARTIN EUGENIO;ROSSI, DANIELE;METRA, CECILIA
2016

Abstract

In this paper, we analyze the effects of aging mechanisms on the soft error susceptibility of both standard and robust latches. Particularly, we consider bias temperature instability (BTI) affecting both nMOS (positive BTI) and pMOS (negative BTI), which is considered the most critical aging mechanism threatening the reliability of ICs. Our analyses show that as an IC ages, BTI significantly increases the susceptibility of both standard latches and low-cost robust latches, whose robustness is based on the increase in the critical charge of their most susceptible node(s). Instead, we will show that BTI minimally affects the soft error susceptibility of more costly robust latches that avoid the generation of soft errors by design. Consequently, our analysis highlights the fact that in applications mandating the use of low-cost robust latches, designers will have to face the problem of their robustness degradation during IC lifetime. Therefore, for these applications, designers will have to develop proper low-cost solutions to guarantee the minimal required level of robustness during the whole IC lifetime.
IEEE TRANSACTIONS ON NANOTECHNOLOGY
Omana, MARTIN EUGENIO; Rossi, Daniele; Edara, T.; Metra, Cecilia
File in questo prodotto:
Eventuali allegati, non sono esposti

I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.

Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11585/541218
 Attenzione

Attenzione! I dati visualizzati non sono stati sottoposti a validazione da parte dell'ateneo

Citazioni
  • ???jsp.display-item.citation.pmc??? ND
  • Scopus 8
  • ???jsp.display-item.citation.isi??? 7
social impact