Analyses recently presented in the literature have shown that the Bias Temperature Instability (BTI) ageing phenomenon may increase significantly the susceptibility to soft errors (SEs) of robust latches. Particularly, this is the case of low-cost robust latches, whose robustness is obtained by increasing the critical charge of their most susceptible node , that is the node most contributing to the latch soft error rate (SER). Therefore, in applications mandating the use of low-cost robust latches, designers will have to face the problem of such latches’ robustness degradation during the IC operation. In order to cope with this problem, we here propose a strategy to reduce the impact of BTI on the SER of standard and low-cost robust latches. It wll be proven that our approach enables to reduce by approximately the 50% the SER increase due to BTI during circuit lifetime with respect to original latches, at limited increase in terms of area overhead, latch setup time and power consumption, and with no impact on the latch input-output delay.
Low-Cost Strategy to Mitigate the Impact of Aging on Latches’ Robustness
OMANA, MARTIN EUGENIO;METRA, CECILIA
2018
Abstract
Analyses recently presented in the literature have shown that the Bias Temperature Instability (BTI) ageing phenomenon may increase significantly the susceptibility to soft errors (SEs) of robust latches. Particularly, this is the case of low-cost robust latches, whose robustness is obtained by increasing the critical charge of their most susceptible node , that is the node most contributing to the latch soft error rate (SER). Therefore, in applications mandating the use of low-cost robust latches, designers will have to face the problem of such latches’ robustness degradation during the IC operation. In order to cope with this problem, we here propose a strategy to reduce the impact of BTI on the SER of standard and low-cost robust latches. It wll be proven that our approach enables to reduce by approximately the 50% the SER increase due to BTI during circuit lifetime with respect to original latches, at limited increase in terms of area overhead, latch setup time and power consumption, and with no impact on the latch input-output delay.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.