In this paper we propose a new robust latch, referred to as HiPeR latch. It is insensitive to TFs affecting its internal and output nodes by design (independently of the size of its transistors), thus being scalable with technology node. It presents better or comparable robustness to TFs compared to the most recent latches in literature, while providing better characteristics in terms of performance at comparable area and power cost.
M. Omaña, D. Rossi, C. Metra (2009). Novel High Speed Robust Latch. LOS ALAMITOS : D. Gizopoulos, M. Tehranipoor, S. Tragoudas [10.1109/DFT.2009.40].
Novel High Speed Robust Latch
OMANA, MARTIN EUGENIO;ROSSI, DANIELE;METRA, CECILIA
2009
Abstract
In this paper we propose a new robust latch, referred to as HiPeR latch. It is insensitive to TFs affecting its internal and output nodes by design (independently of the size of its transistors), thus being scalable with technology node. It presents better or comparable robustness to TFs compared to the most recent latches in literature, while providing better characteristics in terms of performance at comparable area and power cost.File in questo prodotto:
Eventuali allegati, non sono esposti
I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
