This paper reports the main contribution of a project devoted to the definition of techniques to design and evaluate fault tolerant systems implemented using the SoPC paradigm, suitable for missionand safety-critical application environments. In particular, the effort of the five involved research units has been devoted to address some of the main issues related to the specific technological aspects introduced by these flexible platforms. The overall target of the research is the development of a design methodology for highly reliable systems realized on reconfigurable platforms based on a System-on-Programmable Chip (SoPC).

High-reliability Fault Tolerant Digital Systems in Nanometric Technologies: Characterization and Design Methodologies

METRA, CECILIA;OMANA, MARTIN EUGENIO;ROSSI, DANIELE;
2012

Abstract

This paper reports the main contribution of a project devoted to the definition of techniques to design and evaluate fault tolerant systems implemented using the SoPC paradigm, suitable for missionand safety-critical application environments. In particular, the effort of the five involved research units has been devoted to address some of the main issues related to the specific technological aspects introduced by these flexible platforms. The overall target of the research is the development of a design methodology for highly reliable systems realized on reconfigurable platforms based on a System-on-Programmable Chip (SoPC).
Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems
121
125
C. Bolchini; A. Miele; C. Sandionigi; M. Ottavi; S. Pontarelli; A. Salsano; C. Metra; M. Omaña; D. Rossi; M. Sonza Reorda; L. Sterpone; M. Violante; S. Gerardin; M. Bagatin; A. Paccagnella
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11585/134000
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