As device geometries shrink and power supply voltages decrease, simultaneous switching noise has increasingly detrimental effects on IC reliability. The authors investigate the worst-case conditions for SSN generated by a single switching wire and analyze the impact of transition reducing encoding on SSN. They show that switching-pattern and layout considerations have a significant impact on TRE performance.
D. Rossi, A. K. Nieuwland, C. Metra (2008). Simultaneous Switching Noise Analysis: The Relation Between Bus Layout and Coding. IEEE DESIGN & TEST OF COMPUTERS, 25, 76-86 [10.1109/MDT.2008.25].
Simultaneous Switching Noise Analysis: The Relation Between Bus Layout and Coding
ROSSI, DANIELE;METRA, CECILIA
2008
Abstract
As device geometries shrink and power supply voltages decrease, simultaneous switching noise has increasingly detrimental effects on IC reliability. The authors investigate the worst-case conditions for SSN generated by a single switching wire and analyze the impact of transition reducing encoding on SSN. They show that switching-pattern and layout considerations have a significant impact on TRE performance.File in questo prodotto:
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