In this paper we present an on-chip clock jitter digital measurement scheme for high performance microprocessors. The scheme enables in-situ jitter measurement of the clock distribution network during the test or the debug phase. It provides very high measurement resolution, despite the possible presence of power supply noise (constituting a major cause of clock jitter) affecting itself. The resolution is higher than a min sized inverter input-output delay, and can on principle be further increased, at some additional costs in terms of area overhead and power consumption. In this paper, a resolution of the 1.8% of the clock period is achieved with limited area and power costs.
Novel On-Chip Clock Jitter Measurement Scheme For High Performance Microprocessors / C. Metra; M. Omaña; T.M. Mak; A. Rahman; S. Tam. - STAMPA. - (2008), pp. 465-473. (Intervento presentato al convegno The 23rd IEEE International on Defect and Fault Tolerance in VLSI Systems tenutosi a Cambridge (MA), USA nel 1-3 Ottobre 2008).
Novel On-Chip Clock Jitter Measurement Scheme For High Performance Microprocessors
METRA, CECILIA;OMANA, MARTIN EUGENIO;
2008
Abstract
In this paper we present an on-chip clock jitter digital measurement scheme for high performance microprocessors. The scheme enables in-situ jitter measurement of the clock distribution network during the test or the debug phase. It provides very high measurement resolution, despite the possible presence of power supply noise (constituting a major cause of clock jitter) affecting itself. The resolution is higher than a min sized inverter input-output delay, and can on principle be further increased, at some additional costs in terms of area overhead and power consumption. In this paper, a resolution of the 1.8% of the clock period is achieved with limited area and power costs.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
