In this paper, we propose a compact, high-speed, and highly testable parallel two-rail code checker, particularly suitable to implementing embedded checkers. In fact, it requires only two input codewords to satisfy the Totally-Self-Checking or Strongly Code- Disjoint property with respect to a wide set of realistic internal faults. Our checker can be employed to check the correct operation of a connected functional block using the two-rail code, to implement the output two-rail code checker of “normal” checkers for unordered codes, or to join together the error messages produced by various checkers (possibly using different codes) present within the same self-checking system. The behavior of our checker has been verified by means of electrical level simulations (performed using HSPICE), considering both nominal values and statistical variations of electrical parameters. We also propose a possible modification to our checker internal structure that makes it able to provide an output error indication remaining latched until the application of a proper reset signal. Depending on the considered application and recovery technique to be employed upon the generation of an error indication at the checker output, one proposed solution or the other may be preferable.

Low Cost and High Speed Embedded Two-Rail Code Checker

OMANA, MARTIN EUGENIO;ROSSI, DANIELE;METRA, CECILIA
2005

Abstract

In this paper, we propose a compact, high-speed, and highly testable parallel two-rail code checker, particularly suitable to implementing embedded checkers. In fact, it requires only two input codewords to satisfy the Totally-Self-Checking or Strongly Code- Disjoint property with respect to a wide set of realistic internal faults. Our checker can be employed to check the correct operation of a connected functional block using the two-rail code, to implement the output two-rail code checker of “normal” checkers for unordered codes, or to join together the error messages produced by various checkers (possibly using different codes) present within the same self-checking system. The behavior of our checker has been verified by means of electrical level simulations (performed using HSPICE), considering both nominal values and statistical variations of electrical parameters. We also propose a possible modification to our checker internal structure that makes it able to provide an output error indication remaining latched until the application of a proper reset signal. Depending on the considered application and recovery technique to be employed upon the generation of an error indication at the checker output, one proposed solution or the other may be preferable.
M. Omaña; D. Rossi; C. Metra
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11585/5712
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