CRIS Current Research Information System

CONTI, FRANCESCO
 Distribuzione geografica
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Continente #
NA - Nord America 7.260
AS - Asia 6.595
EU - Europa 4.776
SA - Sud America 375
AF - Africa 332
OC - Oceania 15
Continente sconosciuto - Info sul continente non disponibili 3
Totale 19.356
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Nazione #
US - Stati Uniti d'America 7.033
CN - Cina 1.742
SG - Singapore 1.729
IT - Italia 1.541
VN - Vietnam 1.334
DE - Germania 709
GB - Regno Unito 697
HK - Hong Kong 642
FR - Francia 310
IN - India 289
BR - Brasile 281
SE - Svezia 281
KR - Corea 243
NL - Olanda 233
CA - Canada 187
FI - Finlandia 165
RU - Federazione Russa 143
IE - Irlanda 134
JP - Giappone 128
CI - Costa d'Avorio 114
ES - Italia 106
CH - Svizzera 90
ZA - Sudafrica 84
TW - Taiwan 69
BG - Bulgaria 67
PH - Filippine 66
ID - Indonesia 61
SC - Seychelles 58
AT - Austria 48
TR - Turchia 45
UA - Ucraina 43
PL - Polonia 39
AR - Argentina 38
BE - Belgio 34
TH - Thailandia 34
EE - Estonia 29
GR - Grecia 29
BD - Bangladesh 28
IQ - Iraq 28
JO - Giordania 27
MY - Malesia 22
TG - Togo 21
MX - Messico 20
PK - Pakistan 17
IL - Israele 16
RO - Romania 16
AU - Australia 13
EC - Ecuador 13
CL - Cile 12
DK - Danimarca 11
IR - Iran 11
SA - Arabia Saudita 11
DZ - Algeria 10
UZ - Uzbekistan 10
LB - Libano 9
LT - Lituania 9
CO - Colombia 8
HR - Croazia 8
ET - Etiopia 7
KE - Kenya 7
PE - Perù 7
AE - Emirati Arabi Uniti 6
CR - Costa Rica 6
EG - Egitto 6
GH - Ghana 6
LU - Lussemburgo 6
MA - Marocco 6
PY - Paraguay 6
DO - Repubblica Dominicana 5
NO - Norvegia 5
NP - Nepal 5
OM - Oman 5
VE - Venezuela 5
AZ - Azerbaigian 4
CZ - Repubblica Ceca 4
LV - Lettonia 4
SK - Slovacchia (Repubblica Slovacca) 4
TN - Tunisia 4
BO - Bolivia 3
BY - Bielorussia 3
NG - Nigeria 3
SI - Slovenia 3
A2 - ???statistics.table.value.countryCode.A2??? 2
HU - Ungheria 2
KW - Kuwait 2
KZ - Kazakistan 2
LA - Repubblica Popolare Democratica del Laos 2
MD - Moldavia 2
MN - Mongolia 2
NZ - Nuova Zelanda 2
SV - El Salvador 2
TT - Trinidad e Tobago 2
UY - Uruguay 2
BA - Bosnia-Erzegovina 1
BB - Barbados 1
CG - Congo 1
CU - Cuba 1
CY - Cipro 1
EU - Europa 1
GM - Gambi 1
Totale 19.344
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Città #
Ann Arbor 1.797
Singapore 1.194
Ashburn 585
Hong Kong 583
Southend 488
Hefei 438
Chandler 419
Bologna 378
Fairfield 357
San Jose 328
Santa Clara 325
Ho Chi Minh City 312
Hanoi 281
Munich 259
Seoul 202
Wilmington 184
Woodbridge 177
Beijing 155
Los Angeles 151
Seattle 147
Dublin 134
Princeton 132
Houston 130
Montréal 123
Cambridge 118
Abidjan 114
Helsinki 114
Boardman 111
Turin 109
Dallas 105
Mcallen 103
Lauterbourg 89
Tokyo 85
Milan 84
Buffalo 66
Sofia 66
New York 65
Council Bluffs 60
Rome 54
Dong Ket 51
Frankfurt am Main 51
Berlin 50
Da Nang 50
Haiphong 50
Guangzhou 48
Redmond 48
Medford 47
Nanjing 47
Bengaluru 45
Johannesburg 44
Westminster 41
Chicago 40
Jakarta 37
Redondo Beach 36
Nuremberg 33
Zurich 33
Cesena 32
Shanghai 32
Taipei 32
Amsterdam 30
Florence 30
London 30
San Diego 29
The Dalles 29
São Paulo 28
Amman 27
Paris 27
Dearborn 26
Orem 26
Istanbul 25
Jinan 25
Tianjin 25
Redwood City 24
Brandenburg 23
Brussels 23
Vienna 23
Falls Church 22
Lappeenranta 22
Padova 22
Phoenix 22
Warsaw 22
Lomé 21
Sant Esteve de Palautordera 20
Shenyang 20
Can Tho 19
Modena 19
Changsha 18
Falkenstein 18
Hangzhou 18
Norwalk 18
Zhengzhou 18
Castel Maggiore 17
Ravenna 17
Toronto 17
Bangkok 16
Delft 16
Des Moines 16
Bern 15
Bühl 15
Forlì 15
Totale 12.362
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Nome #
Enabling the Heterogeneous Accelerator Model on Ultra-Low Power Microcontroller Platforms 613
Siracusa: A Low-Power On-Sensor RISC-V SoC for Extended Reality Visual Processing in 16nm CMOS 394
XpulpNN: Accelerating Quantized Neural Networks on RISC-V Processors Through ISA Extensions 372
4.4 A 1.3TOPS/W @ 32GOPS Fully Integrated 10-Core SoC for IoT End-Nodes with 1.7μW Cognitive Wake-Up from MRAM-Based State-Retentive Sleep Mode 330
PULP: A parallel ultra low power platform for next generation IoT applications 325
A mixed-precision RISC-V processor for extreme-edge DNN inference 322
PULP-TrainLib: Enabling On-Device Training for RISC-V Multi-core MCUs Through Performance-Driven Autotuning 315
Robust Real-Time Embedded EMG Recognition Framework Using Temporal Convolutional Networks on a Multicore IoT Processor 299
A Heterogeneous Multi-Core System-on-Chip for Energy Efficient Brain Inspired Computing 290
Work-in-Progress: Quantized NNs as the Definitive solution for inference on low-power ARM MCUs? 281
An IoT Endpoint System-on-Chip for Secure and Energy-Efficient Near-Sensor Analytics 270
Slow and steady wins the race? A comparison of ultra-low-power RISC-V cores for Internet-of-Things applications 270
GAP-8: A RISC-V SoC for AI at the Edge of the IoT 256
A Heterogeneous In-Memory Computing Cluster for Flexible End-to-End Inference of Real-World Deep Neural Networks 254
Accelerated Visual Context Classification on a Low-Power Smartwatch 254
PULP-NN: Accelerating Quantized Neural Networks on Parallel Ultra-Low-Power RISC-V Processors 249
A heterogeneous multi-core system-on-chip for energy efficient brain inspired vision 246
Memory-Latency-Accuracy Trade-Offs for Continual Learning on a RISC-V Extreme-Edge Node 246
PULP-NN: A computing library for quantized neural network inference at the edge on RISC-V based parallel ultra low power clusters 237
Marsellus: A Heterogeneous RISC-V AI-IoT End-Node SoC With 2???8 b DNN Acceleration and 30%-Boost Adaptive Body Biasing 225
Dustin: A 16-Cores Parallel Ultra-Low-Power Cluster With 2b-to-32b Fully Flexible Bit-Precision and Vector Lockstep Execution Mode 223
Enabling mixed-precision quantized neural networks in extreme-edge devices 216
Energy efficient parallel computing on the PULP platform with support for OpenMP 213
Curbing the roofline: a scalable and flexible architecture for CNNs on FPGA 213
Work-in-progress: Dory: Lightweight memory hierarchy management for deep NN inference on iot endnodes 211
Brain-inspired classroom occupancy monitoring on a low-power mobile platform 210
GVSoC: A Highly Configurable, Fast and Accurate Full-Platform Simulator for RISC-V based IoT Processors 210
A 1.15 TOPS/W, 16-Cores Parallel Ultra-Low Power Cluster with 2b-to-32b Fully Flexible Bit-Precision and Vector Lockstep Execution Mode 209
A 64mW DNN-based Visual Navigation Engine for Autonomous Nano-Drones 207
XpulpNN: Enabling Energy Efficient and Flexible Inference of Quantized Neural Networks on RISC-V Based IoT End Nodes 206
A Self-Aware Architecture for PVT Compensation and Power Nap in Near Threshold Processors 205
NEURAghe: Exploiting CPU-FPGA synergies for efficient and flexible CNN inference acceleration on zynQ SoCs 205
A Sim-to-Real Deep Learning-based Framework for Autonomous Nano-drone Racing 204
Toward Attention-based TinyML: A Heterogeneous Accelerated Architecture and Automated Deployment Flow 196
Chipmunk: A systolically scalable 0.9 mm2, 3.08Gop/s/mW @ 1.2 mW accelerator for near-sensor recurrent neural network inference 192
An Open Source and Open Hardware Deep Learning-Powered Visual Navigation Engine for Autonomous Nano-UAVs 188
On-the-fly adaptivity for process networks over shared-memory platforms 186
Energy-efficient vision on the PULP platform for ultra-low power parallel computing 186
An Extreme-Edge TCN-Based Low-Latency Collision-Avoidance Safety System for Industrial Machinery 183
Tightly-coupled hardware support to dynamic parallelism acceleration in embedded shared memory clusters 183
Always-On 674μW@4GOP/s Error Resilient Binary Neural Networks With Aggressive SRAM Voltage Scaling on a 22-nm IoT End-Node 181
Fully Onboard AI-powered Human-Drone Pose Estimation on Ultra-low Power Autonomous Flying Nano-UAVs 180
A Microcontroller is All You Need: Enabling Transformer Execution on Low-Power IoT Endnodes 180
A TinyML Platform for On-Device Continual Learning with Quantized Latent Replays 176
PULP: A Ultra-Low Power Parallel Accelerator for Energy-Efficient and Flexible Embedded Vision 175
Exploring NEURAGHE: A Customizable Template for APSoC-based CNN Inference at the Edge 174
Optimizing BFloat16 Deployment of Tiny Transformers on Ultra-Low Power Extreme Edge SoCs 171
DORY: Automatic End-to-End Deployment of Real-World DNNs on Low-Cost IoT MCUs 170
Darkside: A Heterogeneous RISC-V Compute Cluster for Extreme-Edge On-Chip DNN Inference and Training 168
An Ultra-Low Power Address-Event Sensor Interface for Energy-Proportional Time-To-Information Extraction 168
End-To-end 100-TOPS/W Inference with Analog In-Memory Computing: Are We There Yet? 168
Thermal Image-based CNN's for Ultra-low Power People Recognition 167
Multi-core data analytics SoC with a flexible 1.76 Gbit/s AES-XTS cryptographic accelerator in 65 nm CMOS 165
XNOR Neural Engine: A Hardware Accelerator IP for 21.6-fJ/op Binary Neural Network Inference 165
Lightweight Neural Architecture Search for Temporal Convolutional Networks at the Edge 163
Vega: A Ten-Core SoC for IoT Endnodes with DNN Acceleration and Cognitive Wake-Up from MRAM-Based State-Retentive Sleep Mode 163
End-to-End DNN Inference on a Massively Parallel Analog In Memory Computing Architecture 161
He-P2012: Architectural heterogeneity exploration on a scalable many-core platform 160
Scale up your In-Memory Accelerator: Leveraging Wireless-on-Chip Communication for AIMC-based CNN Inference 159
He-P2012: Performance and Energy Exploration of Architecturally Heterogeneous Many-Cores 159
Optimization and deployment of CNNs at the Edge: The ALOHA experience 158
Hybrid Modular Redundancy: Exploring Modular Redundancy Approaches in RISC-V Multi-Core Computing Clusters for Reliable Processing in Space 157
Synthesis-friendly techniques for tightly-coupled integration of hardware accelerators into shared-memory multi-core clusters 157
Improving Autonomous Nano-Drones Performance via Automated End-to-End Optimization and Deployment of DNNs 157
A Ultra-Low-Energy Convolution Engine for Fast Brain-Inspired Vision in Multicore Clusters 156
Siracusa: A 16 nm Heterogenous RISC-V SoC for Extended Reality With At-MRAM Neural Engine 153
Deeploy: Enabling Energy-Efficient Deployment of Small Language Models on Heterogeneous Microcontrollers 153
SNE: an Energy-Proportional Digital Accelerator for Sparse Event-Based Convolutions 151
A 3 TOPS/W RISC-V Parallel Cluster for Inference of Fine-Grain Mixed-Precision Quantized Neural Networks 151
ALOHA: An Architectural-aware Framework for Deep Learning at the Edge 146
RedMule: A mixed-precision matrix–matrix operation engine for flexible and energy-efficient on-chip linear algebra and TinyML training acceleration 143
Online process transformation for polyhedral process networks in shared-memory MPSoCs 143
Quentin: an ultra-low-power PULPissimo SoC in 22nm FDX 141
Distilling Tiny and Ultrafast Deep Neural Networks for Autonomous Navigation on Nano-UAVs 139
Pruning in Time (PIT): A Lightweight Network Architecture Optimizer for Temporal Convolutional Networks 138
Free Bits: Latency Optimization of Mixed-Precision Quantized Neural Networks on the Edge 137
Graphene-based Wireless Agile Interconnects for Massive Heterogeneous Multi-chip Processors 136
Temporal Variability Analysis in sEMG Hand Grasp Recognition using Temporal Convolutional Networks 130
TCN Mapping Optimization for Ultra-Low Power Time-Series Edge Inference 126
Pushing On-chip Memories Beyond Reliability Boundaries in Micropower Machine Learning Applications 123
Darkside: 2.6GFLOPS, 8.7mW Heterogeneous RISC-V Cluster for Extreme-Edge On-Chip DNN Inference and Training 118
22.1 A 12.4TOPS/W @ 136GOPS AI-IoT System-on-Chip with 16 RISC-V, 2-to-8b Precision-Scalable DNN Acceleration and 30%-Boost Adaptive Body Biasing 116
Maestro: A 302 GFLOPS/W and 19.8GFLOPS RISC-V Vector-Tensor Architecture for Wearable Ultrasound Edge Computing 114
AI-Powered Collision Avoidance Safety System for Industrial Woodworking Machinery 111
sEMG Neural Spikes Reconstruction for Gesture Recognition on a Low-Power Multicore Processor. In: Biomedical Circuits and Systems 107
RISC-V Processor Technologies for Aerospace Applications in the ISOLDE Project 103
Vau Da Muntanialas: Energy-Efficient Multi-Die Scalable Acceleration of RNN Inference 103
Accelerating Image-based Pest Detection on a Heterogeneous Multicore Microcontroller 100
Architecting more than Moore: wireless plasticity for massive heterogeneous computer architectures (WiPLASH) 100
Graphene-based Wireless Agile Interconnects for Massive Heterogeneous Multi-chip Processors 99
ECHOES: a 200 GOPS/W Frequency Domain SoC with FFT Processor and I2S DSP for Flexible Data Acquisition from Microphone Arrays 99
A RISC-V-based FPGA Overlay to Simplify Embedded Accelerator Deployment 97
Fünfiiber-Drone: A Modular Open-Platform 18-grams Autonomous Nano-Drone 94
Structured Sparse Back-propagation for Lightweight On-Device Continual Learning on Microcontroller Units 93
A Multi-Precision Bit-Serial Hardware Accelerator IP for Deep Learning Enabled Internet-of-Things 93
Motor-Unit Ordering of Blindly-Separated Surface-EMG Signals for Gesture Recognition 92
A Reliable, Time-Predictable Heterogeneous SoC for AI-Enhanced Mixed-Criticality Edge Applications 91
RNN-Based Radio Resource Management on Multicore RISC-V Accelerator Architectures 91
Reduced precision floating-point optimization for Deep Neural Network On-Device Learning on microcontrollers 90
Open Source Heterogeneous SoCs for Artificial Intelligence: The PULP Platform experience 88
Totale 18.361
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Categoria #
all - tutte 48.727
article - articoli 0
book - libri 0
conference - conferenze 0
curatela - curatele 0
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 0
Totale 48.727
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2020/2021364 0 0 0 0 0 0 0 0 0 102 45 217
2021/20223.228 128 37 304 270 338 249 336 392 411 141 357 265
2022/20231.817 213 224 97 172 148 165 45 99 302 63 208 81
2023/2024907 31 98 66 60 103 116 102 52 28 92 75 84
2024/20253.523 139 389 340 220 463 184 270 236 109 190 253 730
2025/20267.341 588 779 672 545 864 403 964 398 1.519 609 0 0
Totale 19.795