CRIS Current Research Information System

CONTI, FRANCESCO
 Distribuzione geografica
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Continente #
NA - Nord America 5.710
EU - Europa 3.909
AS - Asia 2.317
AF - Africa 148
SA - Sud America 57
OC - Oceania 10
Continente sconosciuto - Info sul continente non disponibili 3
Totale 12.154
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Nazione #
US - Stati Uniti d'America 5.549
IT - Italia 1.203
CN - Cina 689
DE - Germania 653
GB - Regno Unito 647
SG - Singapore 578
HK - Hong Kong 352
SE - Svezia 260
VN - Vietnam 255
FR - Francia 187
IN - India 166
NL - Olanda 165
CA - Canada 157
RU - Federazione Russa 129
FI - Finlandia 126
IE - Irlanda 122
CH - Svizzera 82
CI - Costa d'Avorio 81
KR - Corea 75
BG - Bulgaria 66
ES - Italia 55
BR - Brasile 49
JP - Giappone 38
AT - Austria 37
UA - Ucraina 34
ZA - Sudafrica 34
ID - Indonesia 33
EE - Estonia 29
TR - Turchia 29
JO - Giordania 26
BE - Belgio 25
PL - Polonia 23
TG - Togo 21
GR - Grecia 18
PH - Filippine 15
IL - Israele 10
IR - Iran 10
RO - Romania 10
TW - Taiwan 10
AU - Australia 8
HR - Croazia 8
LB - Libano 7
MY - Malesia 7
DZ - Algeria 6
LT - Lituania 6
LU - Lussemburgo 6
DK - Danimarca 5
CZ - Repubblica Ceca 4
AE - Emirati Arabi Uniti 3
PE - Perù 3
SI - Slovenia 3
TH - Thailandia 3
UZ - Uzbekistan 3
A2 - ???statistics.table.value.countryCode.A2??? 2
AR - Argentina 2
CL - Cile 2
EG - Egitto 2
LV - Lettonia 2
NO - Norvegia 2
NZ - Nuova Zelanda 2
BB - Barbados 1
BD - Bangladesh 1
CO - Colombia 1
CY - Cipro 1
DO - Repubblica Dominicana 1
EU - Europa 1
HU - Ungheria 1
IQ - Iraq 1
JM - Giamaica 1
KE - Kenya 1
KZ - Kazakistan 1
LA - Repubblica Popolare Democratica del Laos 1
LK - Sri Lanka 1
MA - Marocco 1
MU - Mauritius 1
MX - Messico 1
NG - Nigeria 1
OM - Oman 1
PK - Pakistan 1
SK - Slovacchia (Repubblica Slovacca) 1
Totale 12.154
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Città #
Ann Arbor 1.797
Singapore 495
Southend 488
Chandler 419
Fairfield 357
Hong Kong 332
Santa Clara 304
Bologna 291
Munich 250
Ashburn 241
Wilmington 184
Woodbridge 177
Seattle 145
Princeton 132
Houston 125
Montréal 123
Dublin 122
Cambridge 118
Boardman 109
Hefei 109
Mcallen 103
Turin 102
Helsinki 101
Abidjan 81
Milan 72
Sofia 66
Seoul 60
Dong Ket 51
Redmond 48
Medford 47
Berlin 46
Rome 42
Westminster 41
Nanjing 39
Los Angeles 34
Ho Chi Minh City 32
Jakarta 32
Cesena 31
Hanoi 31
New York 29
San Diego 29
Frankfurt am Main 28
Zurich 27
Amman 26
Dearborn 26
Florence 26
Nuremberg 26
Jinan 24
Redwood City 24
Shanghai 23
Brandenburg 22
Falls Church 22
Guangzhou 22
Padova 22
Lomé 21
Chicago 20
Sant Esteve de Palautordera 20
Shenyang 20
Beijing 19
Istanbul 19
Paris 19
Vienna 19
Falkenstein 18
London 18
Norwalk 18
Ravenna 17
Tokyo 17
Brussels 16
Changsha 16
Amsterdam 15
Bern 15
Bühl 15
Forlì 15
Saint Petersburg 15
San Lazzaro di Savena 15
Tongling 14
Bagnacavallo 13
Castel Maggiore 13
Des Moines 13
Modena 13
Tianjin 13
Toronto 13
Warsaw 13
Boydton 12
Duncan 12
Hangzhou 12
Kansas City 12
Nanchang 12
Phoenix 12
Wuhan 12
Zhengzhou 12
Cagliari 11
Hebei 11
Trieste 11
Washington 11
Davao City 9
Fremont 9
Jiaxing 9
Ottawa 9
São Paulo 9
Totale 8.410
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Nome #
Enabling the Heterogeneous Accelerator Model on Ultra-Low Power Microcontroller Platforms 588
Siracusa: A Low-Power On-Sensor RISC-V SoC for Extended Reality Visual Processing in 16nm CMOS 322
PULP: A parallel ultra low power platform for next generation IoT applications 289
A mixed-precision RISC-V processor for extreme-edge DNN inference 253
4.4 A 1.3TOPS/W @ 32GOPS Fully Integrated 10-Core SoC for IoT End-Nodes with 1.7μW Cognitive Wake-Up from MRAM-Based State-Retentive Sleep Mode 231
Robust Real-Time Embedded EMG Recognition Framework Using Temporal Convolutional Networks on a Multicore IoT Processor 221
Slow and steady wins the race? A comparison of ultra-low-power RISC-V cores for Internet-of-Things applications 219
Accelerated Visual Context Classification on a Low-Power Smartwatch 217
Work-in-Progress: Quantized NNs as the Definitive solution for inference on low-power ARM MCUs? 208
XpulpNN: Accelerating Quantized Neural Networks on RISC-V Processors Through ISA Extensions 197
An IoT Endpoint System-on-Chip for Secure and Energy-Efficient Near-Sensor Analytics 196
A Heterogeneous Multi-Core System-on-Chip for Energy Efficient Brain Inspired Computing 187
Energy efficient parallel computing on the PULP platform with support for OpenMP 185
PULP-NN: Accelerating Quantized Neural Networks on Parallel Ultra-Low-Power RISC-V Processors 183
A heterogeneous multi-core system-on-chip for energy efficient brain inspired vision 181
Enabling mixed-precision quantized neural networks in extreme-edge devices 179
Memory-Latency-Accuracy Trade-Offs for Continual Learning on a RISC-V Extreme-Edge Node 172
Brain-inspired classroom occupancy monitoring on a low-power mobile platform 172
PULP-TrainLib: Enabling On-Device Training for RISC-V Multi-core MCUs Through Performance-Driven Autotuning 168
A 64mW DNN-based Visual Navigation Engine for Autonomous Nano-Drones 166
Chipmunk: A systolically scalable 0.9 mm2, 3.08Gop/s/mW @ 1.2 mW accelerator for near-sensor recurrent neural network inference 165
An Open Source and Open Hardware Deep Learning-Powered Visual Navigation Engine for Autonomous Nano-UAVs 161
NEURAghe: Exploiting CPU-FPGA synergies for efficient and flexible CNN inference acceleration on zynQ SoCs 159
Energy-efficient vision on the PULP platform for ultra-low power parallel computing 159
On-the-fly adaptivity for process networks over shared-memory platforms 158
PULP-NN: A computing library for quantized neural network inference at the edge on RISC-V based parallel ultra low power clusters 154
Curbing the roofline: a scalable and flexible architecture for CNNs on FPGA 153
Work-in-progress: Dory: Lightweight memory hierarchy management for deep NN inference on iot endnodes 151
Tightly-coupled hardware support to dynamic parallelism acceleration in embedded shared memory clusters 148
PULP: A Ultra-Low Power Parallel Accelerator for Energy-Efficient and Flexible Embedded Vision 147
Always-On 674μW@4GOP/s Error Resilient Binary Neural Networks With Aggressive SRAM Voltage Scaling on a 22-nm IoT End-Node 147
A Self-Aware Architecture for PVT Compensation and Power Nap in Near Threshold Processors 145
GAP-8: A RISC-V SoC for AI at the Edge of the IoT 143
Multi-core data analytics SoC with a flexible 1.76 Gbit/s AES-XTS cryptographic accelerator in 65 nm CMOS 141
He-P2012: Architectural heterogeneity exploration on a scalable many-core platform 140
Thermal Image-based CNN's for Ultra-low Power People Recognition 140
XNOR Neural Engine: A Hardware Accelerator IP for 21.6-fJ/op Binary Neural Network Inference 138
An Ultra-Low Power Address-Event Sensor Interface for Energy-Proportional Time-To-Information Extraction 137
Exploring NEURAGHE: A Customizable Template for APSoC-based CNN Inference at the Edge 136
GVSoC: A Highly Configurable, Fast and Accurate Full-Platform Simulator for RISC-V based IoT Processors 135
Fully Onboard AI-powered Human-Drone Pose Estimation on Ultra-low Power Autonomous Flying Nano-UAVs 132
A Microcontroller is All You Need: Enabling Transformer Execution on Low-Power IoT Endnodes 132
Synthesis-friendly techniques for tightly-coupled integration of hardware accelerators into shared-memory multi-core clusters 131
A Ultra-Low-Energy Convolution Engine for Fast Brain-Inspired Vision in Multicore Clusters 131
XpulpNN: Enabling Energy Efficient and Flexible Inference of Quantized Neural Networks on RISC-V Based IoT End Nodes 131
A 1.15 TOPS/W, 16-Cores Parallel Ultra-Low Power Cluster with 2b-to-32b Fully Flexible Bit-Precision and Vector Lockstep Execution Mode 129
ALOHA: An Architectural-aware Framework for Deep Learning at the Edge 125
He-P2012: Performance and Energy Exploration of Architecturally Heterogeneous Many-Cores 124
A Heterogeneous In-Memory Computing Cluster for Flexible End-to-End Inference of Real-World Deep Neural Networks 121
DORY: Automatic End-to-End Deployment of Real-World DNNs on Low-Cost IoT MCUs 118
Dustin: A 16-Cores Parallel Ultra-Low-Power Cluster With 2b-to-32b Fully Flexible Bit-Precision and Vector Lockstep Execution Mode 117
Optimization and deployment of CNNs at the Edge: The ALOHA experience 116
Online process transformation for polyhedral process networks in shared-memory MPSoCs 114
Temporal Variability Analysis in sEMG Hand Grasp Recognition using Temporal Convolutional Networks 111
A TinyML Platform for On-Device Continual Learning with Quantized Latent Replays 111
Improving Autonomous Nano-Drones Performance via Automated End-to-End Optimization and Deployment of DNNs 110
Vega: A Ten-Core SoC for IoT Endnodes with DNN Acceleration and Cognitive Wake-Up from MRAM-Based State-Retentive Sleep Mode 109
Quentin: an ultra-low-power PULPissimo SoC in 22nm FDX 108
An Extreme-Edge TCN-Based Low-Latency Collision-Avoidance Safety System for Industrial Machinery 102
End-To-end 100-TOPS/W Inference with Analog In-Memory Computing: Are We There Yet? 102
Pushing On-chip Memories Beyond Reliability Boundaries in Micropower Machine Learning Applications 99
Pruning in Time (PIT): A Lightweight Network Architecture Optimizer for Temporal Convolutional Networks 87
A Sim-to-Real Deep Learning-based Framework for Autonomous Nano-drone Racing 83
Darkside: A Heterogeneous RISC-V Compute Cluster for Extreme-Edge On-Chip DNN Inference and Training 83
Marsellus: A Heterogeneous RISC-V AI-IoT End-Node SoC With 2???8 b DNN Acceleration and 30%-Boost Adaptive Body Biasing 82
Hybrid Modular Redundancy: Exploring Modular Redundancy Approaches in RISC-V Multi-Core Computing Clusters for Reliable Processing in Space 79
TCN Mapping Optimization for Ultra-Low Power Time-Series Edge Inference 79
Darkside: 2.6GFLOPS, 8.7mW Heterogeneous RISC-V Cluster for Extreme-Edge On-Chip DNN Inference and Training 77
Scale up your In-Memory Accelerator: Leveraging Wireless-on-Chip Communication for AIMC-based CNN Inference 76
SNE: an Energy-Proportional Digital Accelerator for Sparse Event-Based Convolutions 76
End-to-End DNN Inference on a Massively Parallel Analog In Memory Computing Architecture 76
AI-Powered Collision Avoidance Safety System for Industrial Woodworking Machinery 74
Lightweight Neural Architecture Search for Temporal Convolutional Networks at the Edge 73
Architecting more than Moore: wireless plasticity for massive heterogeneous computer architectures (WiPLASH) 70
Vau Da Muntanialas: Energy-Efficient Multi-Die Scalable Acceleration of RNN Inference 68
Siracusa: A 16 nm Heterogenous RISC-V SoC for Extended Reality With At-MRAM Neural Engine 65
A Multi-Precision Bit-Serial Hardware Accelerator IP for Deep Learning Enabled Internet-of-Things 64
Motor-Unit Ordering of Blindly-Separated Surface-EMG Signals for Gesture Recognition 63
Toward Attention-based TinyML: A Heterogeneous Accelerated Architecture and Automated Deployment Flow 58
To buffer, or not to buffer? A case study on FFT accelerators for ultra-low-power multicore clusters 58
Fünfiiber-Drone: A Modular Open-Platform 18-grams Autonomous Nano-Drone 58
Graphene-based Wireless Agile Interconnects for Massive Heterogeneous Multi-chip Processors 57
Optimizing BFloat16 Deployment of Tiny Transformers on Ultra-Low Power Extreme Edge SoCs 57
A RISC-V-based FPGA Overlay to Simplify Embedded Accelerator Deployment 57
sEMG Neural Spikes Reconstruction for Gesture Recognition on a Low-Power Multicore Processor. In: Biomedical Circuits and Systems 55
RedMule: A mixed-precision matrix–matrix operation engine for flexible and energy-efficient on-chip linear algebra and TinyML training acceleration 54
RISC-V Processor Technologies for Aerospace Applications in the ISOLDE Project 52
RNN-Based Radio Resource Management on Multicore RISC-V Accelerator Architectures 52
Free Bits: Latency Optimization of Mixed-Precision Quantized Neural Networks on the Edge 48
Distilling Tiny and Ultrafast Deep Neural Networks for Autonomous Navigation on Nano-UAVs 48
Deeploy: Enabling Energy-Efficient Deployment of Small Language Models on Heterogeneous Microcontrollers 47
ECHOES: a 200 GOPS/W Frequency Domain SoC with FFT Processor and I2S DSP for Flexible Data Acquisition from Microphone Arrays 47
Graphene-based Wireless Agile Interconnects for Massive Heterogeneous Multi-chip Processors 46
Reduced precision floating-point optimization for Deep Neural Network On-Device Learning on microcontrollers 45
TCN Mapping Optimization for Ultra-Low Power Time-Series Edge Inference 42
RedMulE: A Compact FP16 Matrix-Multiplication Accelerator for Adaptive Deep Learning on RISC-V-Based Ultra-Low-Power SoCs 42
HTVM: Efficient Neural Network Deployment On Heterogeneous TinyML Platforms 42
22.1 A 12.4TOPS/W @ 136GOPS AI-IoT System-on-Chip with 16 RISC-V, 2-to-8b Precision-Scalable DNN Acceleration and 30%-Boost Adaptive Body Biasing 42
WIP: Automatic DNN Deployment on Heterogeneous Platforms: The GAP9 Case Study 42
Specialization meets Flexibility: a Heterogeneous Architecture for High-Efficiency, High-flexibility AR/VR Processing 37
Totale 12.325
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Categoria #
all - tutte 34.336
article - articoli 0
book - libri 0
conference - conferenze 0
curatela - curatele 0
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 0
Totale 34.336
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2020/2021974 168 50 31 39 48 64 47 47 116 102 45 217
2021/20223.228 128 37 304 270 338 249 336 392 411 141 357 265
2022/20231.817 213 224 97 172 148 165 45 99 302 63 208 81
2023/2024907 31 98 66 60 103 116 102 52 28 92 75 84
2024/20253.523 139 389 340 220 463 184 270 236 109 190 253 730
2025/202666 66 0 0 0 0 0 0 0 0 0 0 0
Totale 12.520