CRIS Current Research Information System

CONTI, FRANCESCO
 Distribuzione geografica
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Continente #
NA - Nord America 5.189
EU - Europa 2.935
AS - Asia 1.197
AF - Africa 138
SA - Sud America 19
OC - Oceania 8
Continente sconosciuto - Info sul continente non disponibili 3
Totale 9.489
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Nazione #
US - Stati Uniti d'America 5.039
IT - Italia 916
GB - Regno Unito 626
DE - Germania 450
CN - Cina 405
SG - Singapore 328
SE - Svezia 254
IN - India 156
CA - Canada 149
VN - Vietnam 143
IE - Irlanda 115
FR - Francia 111
CH - Svizzera 71
CI - Costa d'Avorio 71
BG - Bulgaria 66
FI - Finlandia 57
RU - Federazione Russa 49
ES - Italia 46
NL - Olanda 34
ZA - Sudafrica 34
EE - Estonia 29
UA - Ucraina 29
JP - Giappone 27
JO - Giordania 26
TR - Turchia 26
HK - Hong Kong 24
BE - Belgio 22
TG - Togo 21
GR - Grecia 15
PH - Filippine 15
BR - Brasile 13
AT - Austria 12
IR - Iran 10
HR - Croazia 8
KR - Corea 7
LB - Libano 7
PL - Polonia 7
TW - Taiwan 7
AU - Australia 6
DZ - Algeria 6
IL - Israele 4
MY - Malesia 4
RO - Romania 4
SI - Slovenia 3
A2 - ???statistics.table.value.countryCode.A2??? 2
AR - Argentina 2
CL - Cile 2
CZ - Repubblica Ceca 2
DK - Danimarca 2
EG - Egitto 2
ID - Indonesia 2
NO - Norvegia 2
NZ - Nuova Zelanda 2
UZ - Uzbekistan 2
AE - Emirati Arabi Uniti 1
CO - Colombia 1
DO - Repubblica Dominicana 1
EU - Europa 1
HU - Ungheria 1
KE - Kenya 1
KZ - Kazakistan 1
LA - Repubblica Popolare Democratica del Laos 1
LT - Lituania 1
LU - Lussemburgo 1
LV - Lettonia 1
MA - Marocco 1
MU - Mauritius 1
NG - Nigeria 1
PE - Perù 1
SK - Slovacchia (Repubblica Slovacca) 1
TH - Thailandia 1
Totale 9.489
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Città #
Ann Arbor 1.797
Southend 488
Chandler 419
Fairfield 357
Singapore 287
Ashburn 218
Bologna 190
Wilmington 184
Woodbridge 177
Seattle 145
Munich 132
Princeton 132
Houston 125
Montréal 123
Cambridge 118
Dublin 115
Mcallen 103
Turin 88
Abidjan 71
Sofia 66
Milan 54
Santa Clara 54
Dong Ket 51
Redmond 48
Medford 47
Berlin 46
Helsinki 45
Westminster 41
Nanjing 38
Rome 29
San Diego 29
Amman 26
Dearborn 26
New York 26
Los Angeles 25
Redwood City 24
Florence 23
Jinan 23
Falls Church 22
Padova 22
Lomé 21
Chicago 20
Sant Esteve de Palautordera 20
Zurich 20
Guangzhou 19
Shanghai 19
Shenyang 19
Istanbul 18
Norwalk 18
Beijing 16
Bern 15
Brussels 15
Bühl 15
Nuremberg 15
Ravenna 15
Saint Petersburg 15
Frankfurt am Main 14
Bagnacavallo 13
Des Moines 13
Hangzhou 13
Modena 13
Boydton 12
Changsha 12
Duncan 12
Nanchang 12
San Lazzaro di Savena 12
Cagliari 11
Castel Maggiore 11
Hebei 11
Tianjin 11
Washington 11
Davao City 10
Paris 10
Fremont 9
Jiaxing 9
Phoenix 9
Tokyo 9
Toronto 9
Verona 9
Wuhan 9
Zhengzhou 9
Forlì 8
Johannesburg 8
London 8
Tappahannock 8
Amsterdam 7
Boardman 7
Haikou 7
Hong Kong 7
Kolkata 7
Leawood 7
Ningbo 7
Ottawa 7
Trento 7
Cesena 6
Ferrara 6
Lappeenranta 6
Mountain View 6
San Giovanni in Persiceto 6
Sankt Augustin 6
Totale 6.718
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Nome #
Enabling the Heterogeneous Accelerator Model on Ultra-Low Power Microcontroller Platforms 579
PULP: A parallel ultra low power platform for next generation IoT applications 263
A mixed-precision RISC-V processor for extreme-edge DNN inference 233
4.4 A 1.3TOPS/W @ 32GOPS Fully Integrated 10-Core SoC for IoT End-Nodes with 1.7μW Cognitive Wake-Up from MRAM-Based State-Retentive Sleep Mode 212
Accelerated Visual Context Classification on a Low-Power Smartwatch 202
Slow and steady wins the race? A comparison of ultra-low-power RISC-V cores for Internet-of-Things applications 201
Work-in-Progress: Quantized NNs as the Definitive solution for inference on low-power ARM MCUs? 192
Robust Real-Time Embedded EMG Recognition Framework Using Temporal Convolutional Networks on a Multicore IoT Processor 190
XpulpNN: Accelerating Quantized Neural Networks on RISC-V Processors Through ISA Extensions 187
An IoT Endpoint System-on-Chip for Secure and Energy-Efficient Near-Sensor Analytics 176
Energy efficient parallel computing on the PULP platform with support for OpenMP 171
A Heterogeneous Multi-Core System-on-Chip for Energy Efficient Brain Inspired Computing 168
PULP-NN: Accelerating Quantized Neural Networks on Parallel Ultra-Low-Power RISC-V Processors 164
Enabling mixed-precision quantized neural networks in extreme-edge devices 164
Brain-inspired classroom occupancy monitoring on a low-power mobile platform 162
Chipmunk: A systolically scalable 0.9 mm2, 3.08Gop/s/mW @ 1.2 mW accelerator for near-sensor recurrent neural network inference 157
A 64mW DNN-based Visual Navigation Engine for Autonomous Nano-Drones 152
An Open Source and Open Hardware Deep Learning-Powered Visual Navigation Engine for Autonomous Nano-UAVs 150
On-the-fly adaptivity for process networks over shared-memory platforms 146
NEURAghe: Exploiting CPU-FPGA synergies for efficient and flexible CNN inference acceleration on zynQ SoCs 145
A heterogeneous multi-core system-on-chip for energy efficient brain inspired vision 145
Memory-Latency-Accuracy Trade-Offs for Continual Learning on a RISC-V Extreme-Edge Node 145
Curbing the roofline: a scalable and flexible architecture for CNNs on FPGA 144
Energy-efficient vision on the PULP platform for ultra-low power parallel computing 143
Always-On 674μW@4GOP/s Error Resilient Binary Neural Networks With Aggressive SRAM Voltage Scaling on a 22-nm IoT End-Node 139
PULP: A Ultra-Low Power Parallel Accelerator for Energy-Efficient and Flexible Embedded Vision 138
Tightly-coupled hardware support to dynamic parallelism acceleration in embedded shared memory clusters 138
A Self-Aware Architecture for PVT Compensation and Power Nap in Near Threshold Processors 135
XNOR Neural Engine: A Hardware Accelerator IP for 21.6-fJ/op Binary Neural Network Inference 132
Thermal Image-based CNN's for Ultra-low Power People Recognition 132
PULP-NN: A computing library for quantized neural network inference at the edge on RISC-V based parallel ultra low power clusters 132
Work-in-progress: Dory: Lightweight memory hierarchy management for deep NN inference on iot endnodes 131
Multi-core data analytics SoC with a flexible 1.76 Gbit/s AES-XTS cryptographic accelerator in 65 nm CMOS 130
An Ultra-Low Power Address-Event Sensor Interface for Energy-Proportional Time-To-Information Extraction 130
He-P2012: Architectural heterogeneity exploration on a scalable many-core platform 127
A Ultra-Low-Energy Convolution Engine for Fast Brain-Inspired Vision in Multicore Clusters 127
GAP-8: A RISC-V SoC for AI at the Edge of the IoT 125
Exploring NEURAGHE: A Customizable Template for APSoC-based CNN Inference at the Edge 123
Synthesis-friendly techniques for tightly-coupled integration of hardware accelerators into shared-memory multi-core clusters 119
ALOHA: An Architectural-aware Framework for Deep Learning at the Edge 117
He-P2012: Performance and Energy Exploration of Architecturally Heterogeneous Many-Cores 115
A Microcontroller is All You Need: Enabling Transformer Execution on Low-Power IoT Endnodes 107
GVSoC: A Highly Configurable, Fast and Accurate Full-Platform Simulator for RISC-V based IoT Processors 107
Online process transformation for polyhedral process networks in shared-memory MPSoCs 105
Optimization and deployment of CNNs at the Edge: The ALOHA experience 104
Quentin: an ultra-low-power PULPissimo SoC in 22nm FDX 101
Fully Onboard AI-powered Human-Drone Pose Estimation on Ultra-low Power Autonomous Flying Nano-UAVs 101
A 1.15 TOPS/W, 16-Cores Parallel Ultra-Low Power Cluster with 2b-to-32b Fully Flexible Bit-Precision and Vector Lockstep Execution Mode 101
PULP-TrainLib: Enabling On-Device Training for RISC-V Multi-core MCUs Through Performance-Driven Autotuning 100
Temporal Variability Analysis in sEMG Hand Grasp Recognition using Temporal Convolutional Networks 99
DORY: Automatic End-to-End Deployment of Real-World DNNs on Low-Cost IoT MCUs 96
XpulpNN: Enabling Energy Efficient and Flexible Inference of Quantized Neural Networks on RISC-V Based IoT End Nodes 95
Pushing On-chip Memories Beyond Reliability Boundaries in Micropower Machine Learning Applications 92
Vega: A Ten-Core SoC for IoT Endnodes with DNN Acceleration and Cognitive Wake-Up from MRAM-Based State-Retentive Sleep Mode 87
End-To-end 100-TOPS/W Inference with Analog In-Memory Computing: Are We There Yet? 86
A TinyML Platform for On-Device Continual Learning with Quantized Latent Replays 78
Improving Autonomous Nano-Drones Performance via Automated End-to-End Optimization and Deployment of DNNs 75
Pruning in Time (PIT): A Lightweight Network Architecture Optimizer for Temporal Convolutional Networks 72
A Heterogeneous In-Memory Computing Cluster for Flexible End-to-End Inference of Real-World Deep Neural Networks 69
Dustin: A 16-Cores Parallel Ultra-Low-Power Cluster With 2b-to-32b Fully Flexible Bit-Precision and Vector Lockstep Execution Mode 68
Siracusa: A Low-Power On-Sensor RISC-V SoC for Extended Reality Visual Processing in 16nm CMOS 62
An Extreme-Edge TCN-Based Low-Latency Collision-Avoidance Safety System for Industrial Machinery 60
Architecting more than Moore: wireless plasticity for massive heterogeneous computer architectures (WiPLASH) 60
AI-Powered Collision Avoidance Safety System for Industrial Woodworking Machinery 60
TCN Mapping Optimization for Ultra-Low Power Time-Series Edge Inference 58
A Multi-Precision Bit-Serial Hardware Accelerator IP for Deep Learning Enabled Internet-of-Things 56
Vau Da Muntanialas: Energy-Efficient Multi-Die Scalable Acceleration of RNN Inference 55
SNE: an Energy-Proportional Digital Accelerator for Sparse Event-Based Convolutions 48
A RISC-V-based FPGA Overlay to Simplify Embedded Accelerator Deployment 44
Fünfiiber-Drone: A Modular Open-Platform 18-grams Autonomous Nano-Drone 44
RNN-Based Radio Resource Management on Multicore RISC-V Accelerator Architectures 43
Scale up your In-Memory Accelerator: Leveraging Wireless-on-Chip Communication for AIMC-based CNN Inference 42
Motor-Unit Ordering of Blindly-Separated Surface-EMG Signals for Gesture Recognition 42
To buffer, or not to buffer? A case study on FFT accelerators for ultra-low-power multicore clusters 42
Darkside: A Heterogeneous RISC-V Compute Cluster for Extreme-Edge On-Chip DNN Inference and Training 40
sEMG Neural Spikes Reconstruction for Gesture Recognition on a Low-Power Multicore Processor. In: Biomedical Circuits and Systems 35
End-to-End DNN Inference on a Massively Parallel Analog In Memory Computing Architecture 34
Darkside: 2.6GFLOPS, 8.7mW Heterogeneous RISC-V Cluster for Extreme-Edge On-Chip DNN Inference and Training 33
RISC-V Processor Technologies for Aerospace Applications in the ISOLDE Project 31
Lightweight Neural Architecture Search for Temporal Convolutional Networks at the Edge 31
A 3 TOPS/W RISC-V Parallel Cluster for Inference of Fine-Grain Mixed-Precision Quantized Neural Networks 28
RedMulE: A Compact FP16 Matrix-Multiplication Accelerator for Adaptive Deep Learning on RISC-V-Based Ultra-Low-Power SoCs 27
ECHOES: a 200 GOPS/W Frequency Domain SoC with FFT Processor and I2S DSP for Flexible Data Acquisition from Microphone Arrays 27
Marsellus: A Heterogeneous RISC-V AI-IoT End-Node SoC With 2???8 b DNN Acceleration and 30%-Boost Adaptive Body Biasing 25
A Sim-to-Real Deep Learning-based Framework for Autonomous Nano-drone Racing 25
Specialization meets Flexibility: a Heterogeneous Architecture for High-Efficiency, High-flexibility AR/VR Processing 23
TCN Mapping Optimization for Ultra-Low Power Time-Series Edge Inference 22
Graphene-based Wireless Agile Interconnects for Massive Heterogeneous Multi-chip Processors 21
HTVM: Efficient Neural Network Deployment On Heterogeneous TinyML Platforms 20
Graphene-based Wireless Agile Interconnects for Massive Heterogeneous Multi-chip Processors 19
Hybrid Modular Redundancy: Exploring Modular Redundancy Approaches in RISC-V Multi-Core Computing Clusters for Reliable Processing in Space 18
PULP Fiction No More-Dependable PULP Systems for Space 18
ViT-LR: Pushing the Envelope for Transformer-Based On-Device Embedded Continual Learning 16
RedMule: A mixed-precision matrix–matrix operation engine for flexible and energy-efficient on-chip linear algebra and TinyML training acceleration 15
WIP: Automatic DNN Deployment on Heterogeneous Platforms: The GAP9 Case Study 14
22.1 A 12.4TOPS/W @ 136GOPS AI-IoT System-on-Chip with 16 RISC-V, 2-to-8b Precision-Scalable DNN Acceleration and 30%-Boost Adaptive Body Biasing 13
Reduced precision floating-point optimization for Deep Neural Network On-Device Learning on microcontrollers 12
Free Bits: Latency Optimization of Mixed-Precision Quantized Neural Networks on the Edge 11
null 8
Siracusa: A 16 nm Heterogenous RISC-V SoC for Extended Reality With At-MRAM Neural Engine 4
Totale 9.810
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Categoria #
all - tutte 25.217
article - articoli 0
book - libri 0
conference - conferenze 0
curatela - curatele 0
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 0
Totale 25.217
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2019/20201.314 0 0 46 97 167 155 196 165 182 112 89 105
2020/2021974 168 50 31 39 48 64 47 47 116 102 45 217
2021/20223.228 128 37 304 270 338 249 336 392 411 141 357 265
2022/20231.817 213 224 97 172 148 165 45 99 302 63 208 81
2023/2024918 31 98 66 60 103 116 102 52 30 96 79 85
2024/2025868 143 393 332 0 0 0 0 0 0 0 0 0
Totale 9.810