On-the-fly adaptivity for process networks over shared-memory platforms

Modern MPSoC architectures incorporate tens of processing elements on a single die. This trend poses the need of expressing the parallelism of the applications in order to effectively exploit the available resources. Several models of computation have been proposed, that specify an application as a network of independent computational elements. Such models represent a suitable solution for systematic mapping of parallel applications onto multiprocessor architectures. However, the workload of a given application can abruptly vary, as well as the amount of computing resources available, depending on the overall workload of the system and on the input data dependency. Traditional worst-case designs may overestimate workloads, leading to resource wasting and unnecessary power consumption. To overcome such limitation, in this work we devise a fast, run-time and automatic approach able to quickly re-configure the core-to-task mapping and the degree of parallelism of the application when the available resources or the application workload change, targeting shared-memory platforms. Experiments, carried out using an FPGA implementation, demonstrate the effectiveness of the proposed approach, in terms of achievable speed-up, power saving and introduced overhead.