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ItalianoLOI, IGOR
Dettaglio
LOI, IGOR
DIPARTIMENTO DI INGEGNERIA DELL'ENERGIA ELETTRICA E DELL'INFORMAZIONE "GUGLIELMO MARCONI"
Collaboratori
Igor L.; Loi I.; I. LOI; Igor Loi
Pubblicazioni
Risultati 1 - 20 di 55 (tempo di esecuzione: 0.002 secondi).
| Titolo | Autore(i) | Anno | Periodico | Editore | Tipo | File | |
|---|---|---|---|---|---|---|---|
| 1 | A -1.8V to 0.9V body bias, 60 GOPS/W 4-core cluster in low-power 28nm UTBB FD-SOI technology | Rossi, Davide; Pullini, Antonio; Gautschi, Michael; Loi, Igor; Gurkaynak, Frank Kagan; Flatresse,... Philippe; Benini, Luca | 2015 | Institute of Electrical and Electronics Engineers Inc. | 4.01 Contributo in Atti di convegno | ||
| 2 | 193 MOPS/mW @ 162 MOPS, 0.32V to 1.15V voltage range multi-core accelerator for energy efficient parallel and sequential digital processing | Rossi, Davide; Pullini, Antonio; Loi, Igor; Gautschi, Michael; Gurkaynak, Frank Kagan; Teman, Ada...m; Constantin, Jeremy; Burg, Andreas; Miro-Panades, Ivan; Beign, Edith; Clermidy, Fabien; Abouzeid, Fady; Flatresse, Philippe; Benini, Luca | 2016 | Institute of Electrical and Electronics Engineers Inc. | 4.01 Contributo in Atti di convegno | - | |
| 3 | 3D logarithmic interconnect: Stacking multiple L1 memory dies over multi-core clusters2013 Seventh IEEE/ACM International Symposium on Networks-on-Chip (NoCS) | Erfan Azarkhish;Igor Loi;Luca Benini | 2013 | IEEE | 4.01 Contributo in Atti di convegno | - | |
| 4 | 3D NoCs — Unifying inter & intra chip communication | Loi I. ; Marchal P. ; Pullini A. ; Benini L. | 2010 | IEEE Press | 4.01 Contributo in Atti di convegno | - | |
| 5 | 3D-LIN: A Configurable Low-Latency Interconnect for Multi-Core Clusters with 3D Stacked L1 Memory | G. Beanato; I. Loi; G. De Micheli; Y. Leblebici; L. Benini | 2012 | IEEE Press | 4.01 Contributo in Atti di convegno | - | |
| 6 | 4.4 A 1.3TOPS/W @ 32GOPS Fully Integrated 10-Core SoC for IoT End-Nodes with 1.7μW Cognitive Wake-Up from MRAM-Based State-Retentive Sleep Mode | Rossi D.; Conti F.; Eggiman M.; Mach S.; Mauro A.D.; Guermandi M.; Tagliavini G.; Pullini A.; Loi... I.; Chen J.; Flamand E.; Benini L. | 2021 | Institute of Electrical and Electronics Engineers Inc. | 4.01 Contributo in Atti di convegno | ||
| 7 | A 60 GOPS/W, -1.8 v to 0.9 v body bias ULP cluster in 28 nm UTBB FD-SOI technology | Rossi, Davide; Pullini, Antonio; Loi, Igor; Gautschi, Michael; Gürkaynak, Frank K.; Bartolini, An...drea; Flatresse, Philippe; Benini, Luca | 2016 | SOLID-STATE ELECTRONICS | 1.01 Articolo in rivista | - | |
| 8 | A case for three-dimensional stacking of tightly coupled data memories over multi-core clusters using low-latency interconnects | Erfan Azarkhish;Luca Benini;Igor Loi | 2013 | IET COMPUTERS & DIGITAL TECHNIQUES | 1.01 Articolo in rivista | - | |
| 9 | A fully-synthesizable single-cycle interconnection network for Shared-L1 processor clusters | Rahimi A. ; Loi I. ; Kakoee M.R. ; Benini L. | 2011 | IEEE Press | 4.01 Contributo in Atti di convegno | - | |
| 10 | A high-performance multiported L2 memory IP for scalable three-dimensional integration2013 IEEE International 3D Systems Integration Conference (3DIC) | Erfan Azarkhish;Igor Loi;Luca Benini | 2013 | 2013 IEEE Conference Proceedings | 4.01 Contributo in Atti di convegno | - | |
| 11 | A low-overhead fault tolerance scheme for TSV-based 3D network on chip links. | Loi I.; Mitra S.; Lee T.H.; Fujita S.; Benini L. | 2008 | IEEE | 4.01 Contributo in Atti di convegno | - | |
| 12 | A new physical routing approach for robust bundled signaling on NoC links | M. R. Kakoee; I. Loi; L. Benini | 2010 | ACM | 4.01 Contributo in Atti di convegno | - | |
| 13 | A resilient architecture for low latency communication in shared-L1 processor clusters | Kakoee M.R.; Loi I. ; Benini L. | 2012 | IEEE Press | 4.01 Contributo in Atti di convegno | - | |
| 14 | A shared-FPU architecture for ultra-low power MPSoCs, Proceedings of the ACM International Conference on Computing Frontiers - CF '13 | Mohammad Reza Kakoee;Igor Loi;Luca Benini | 2013 | 4.01 Contributo in Atti di convegno | - | ||
| 15 | Area and Power Modeling for Networks-on-Chip with Layout Awareness | P. Meloni; I. Loi; F. Angiolini; S. Carta; M. Barbaro; L. Raffo; L. Benini | 2007 | VLSI DESIGN | 1.01 Articolo in rivista | - | |
| 16 | Characterization and Implementation of Fault-Tolerant Vertical Links for 3-D Networks-on-Chip | Loi I.; Angiolini F.; Fujita S.; Mitra S.; Benini L. | 2011 | IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS | 1.01 Articolo in rivista | - | |
| 17 | Configurable Low-Latency Interconnect for Multi-core ClustersVLSI-SoC: From Algorithms to Circuits and System-on-Chip Design | Giulia Beanato;Igor Loi;Giovanni De Micheli;Yusuf Leblebici;Luca Benini | 2013 | Springer | 2.01 Capitolo / saggio in libro | - | |
| 18 | Curbing the roofline: a scalable and flexible architecture for CNNs on FPGA | Meloni, Paolo; Deriu, Gianfranco; Conti, Francesco; Loi, Igor; Raffo, Luigi; Benini, Luca | 2016 | ACM | 4.01 Contributo in Atti di convegno | - | |
| 19 | Design and evaluation of a processing-in-memory architecture for the smart memory cube | Azarkhish, Erfan; Rossi, Davide; Loi, Igor; Benini, Luca | 2016 | Springer Verlag | 4.01 Contributo in Atti di convegno | - | |
| 20 | Design Issues and Considerations for Low-Cost 3-D TSV IC Technology | Van der Plas G.; Limaye P.; Loi I.; Mercha A.; Oprins H.; Torregiani C.; Thijs S.; Linten D.; Stu...cchi M.; Katti G.; Velenis D.; Cherman V.; Vandevelde B.; Simons V.; De Wolf I.; Labie R.; Perry D.; Bronckers S.; Minas N.; Cupac M.; Ruythooren W.; Van Olmen J.; Phommahaxay A.; de Potter de ten Broeck M.; Opdebeeck A.; Rakowski M.; De Wachter B.; Dehan M.; Nelis M.; Agarwal R.; Pullini A.; Angiolini F.; Benini L.; Dehaene W.; Travaly Y.; Beyne E.; Marchal P. | 2011 | IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1.01 Articolo in rivista | - |
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