LOI, IGOR
LOI, IGOR
DIPARTIMENTO DI INGEGNERIA DELL'ENERGIA ELETTRICA E DELL'INFORMAZIONE "GUGLIELMO MARCONI"
Collaboratori
Igor L.; Loi I.; I. LOI; Igor Loi
4.4 A 1.3TOPS/W @ 32GOPS Fully Integrated 10-Core SoC for IoT End-Nodes with 1.7μW Cognitive Wake-Up from MRAM-Based State-Retentive Sleep Mode
2021 Rossi D.; Conti F.; Eggiman M.; Mach S.; Mauro A.D.; Guermandi M.; Tagliavini G.; Pullini A.; Loi I.; Chen J.; Flamand E.; Benini L.
Mr.Wolf: An Energy-Precision Scalable Parallel Ultra Low Power SoC for IoT Edge Processing
2019 Pullini A.; Rossi D.; Loi I.; Tagliavini G.; Benini L.
A Heterogeneous Multi-Core System-on-Chip for Energy Efficient Brain Inspired Computing
2018 Pullini, Antonio; Conti, Francesco; Rossi, Davide; Loi, Igor; Gautschi, Michael; Benini, Luca
GAP-8: A RISC-V SoC for AI at the Edge of the IoT
2018 E. Flamand; D. Rossi; F. Conti; I. Loi; A. Pullini; F. Rotenberg; L. Benini
Mr. Wolf: A 1 GFLOP/s Energy-Proportional Parallel Ultra Low Power SoC for IOT Edge Processing
2018 Pullini, Antonio; Rossi, Davide; Loi, Igor; Di Mauro, Alfio; Benini, Luca
Neurostream: Scalable and Energy Efficient Deep Learning with Smart Memory Cubes
2018 Azarkhish, Erfan*; Rossi, Davide; Loi, Igor; Benini, Luca
Sub-mW multi-Gbps chip-to-chip communication Links for Ultra-Low Power IoT end-nodes
2018 Martino, Dazzi; Pierpaolo, Palestri; Davide, Rossi; Andrea, Bandizioly; Igor, Loi; David, Bellasi; Luca, Benini
The Quest for Energy-Efficient I$ Design in Ultra-Low-Power Clustered Many-Cores
2018 Loi, Igor; Capotondi, Alessandro; Rossi, Davide; Marongiu, Andrea; Benini, Luca
A Hybrid Instruction Prefetching Mechanism for Ultra Low-Power Multicore Clusters
2017 Payami, Maryam*; Azarkhish, Erfan; Loi, Igor; Benini, Luca
A Self-Aware Architecture for PVT Compensation and Power Nap in Near Threshold Processors
2017 Rossi, Davide; Loi, Igor; Pullini, Antonio; Muller, Christoph; Burg, Andreas; Conti, Francesco; Benini, Luca; Flatresse, Philippe
An IoT Endpoint System-on-Chip for Secure and Energy-Efficient Near-Sensor Analytics
2017 Conti, Francesco; Schilling, Robert; Schiavone, Pasquale Davide; Pullini, Antonio; Rossi, Davide; Gurkaynak, Frank Kagan; Muehlberghuber, Michael; Gautschi, Michael; Loi, Igor; Haugou, Germain; Mangard, Stefan; Benini, Luca
Energy-Efficient Near-Threshold Parallel Computing: The PULPv2 Cluster
2017 Rossi, Davide; Pullini, Antonio; Loi, Igor; Gautschi, Michael; Gurkaynak, Frank Kagan; Teman, Adam; Constantin, Jeremy; Burg, Andreas; Miro-Panades, Ivan; Beigne, Edith; Clermidy, Fabien; Flatresse, Philippe; Benini, Luca
Logic-Base Interconnect Design for Near Memory Computing in the Smart Memory Cube
2017 Azarkhish, Erfan; Pfister, Christoph; Rossi, Davide; Loi, Igor; Benini, Luca
Near-Threshold RISC-V Core With DSP Extensions for Scalable IoT Endpoint Devices
2017 Gautschi, Michael; Schiavone, Pasquale Davide; Traber, Andreas; Loi, Igor; Pullini, Antonio; Rossi, Davide; Flamand, Eric; Gurkaynak, Frank K.; Benini, Luca
Ultra-Low-Power Digital Architectures for the Internet of Things
2017 Rossi, Davide; Loi, Igor; Pullini, Antonio; Benini, Luca
193 MOPS/mW @ 162 MOPS, 0.32V to 1.15V voltage range multi-core accelerator for energy efficient parallel and sequential digital processing
2016 Rossi, Davide; Pullini, Antonio; Loi, Igor; Gautschi, Michael; Gurkaynak, Frank Kagan; Teman, Adam; Constantin, Jeremy; Burg, Andreas; Miro-Panades, Ivan; Beign, Edith; Clermidy, Fabien; Abouzeid, Fady; Flatresse, Philippe; Benini, Luca
A 60 GOPS/W, -1.8 v to 0.9 v body bias ULP cluster in 28 nm UTBB FD-SOI technology
2016 Rossi, Davide; Pullini, Antonio; Loi, Igor; Gautschi, Michael; Gürkaynak, Frank K.; Bartolini, Andrea; Flatresse, Philippe; Benini, Luca
A heterogeneous multi-core system-on-chip for energy efficient brain inspired vision
2016 Pullini, Antonio; Conti, Francesco; Rossi, Davide; Loi, Igor; Gautschi, Michael; Benini, Luca
Curbing the roofline: a scalable and flexible architecture for CNNs on FPGA
2016 Meloni, Paolo; Deriu, Gianfranco; Conti, Francesco; Loi, Igor; Raffo, Luigi; Benini, Luca
Design and evaluation of a processing-in-memory architecture for the smart memory cube
2016 Azarkhish, Erfan; Rossi, Davide; Loi, Igor; Benini, Luca
| Titolo | Autore(i) | Anno | Periodico | Editore | Tipo | File |
|---|---|---|---|---|---|---|
| 4.4 A 1.3TOPS/W @ 32GOPS Fully Integrated 10-Core SoC for IoT End-Nodes with 1.7μW Cognitive Wake-Up from MRAM-Based State-Retentive Sleep Mode | Rossi D.; Conti F.; Eggiman M.; Mach S.; Mauro A.D.; Guermandi M.; Tagliavini G.; Pullini A.; Loi... I.; Chen J.; Flamand E.; Benini L. | 2021-01-01 | - | Institute of Electrical and Electronics Engineers Inc. | 4.01 Contributo in Atti di convegno | 09365939.pdf; paper_proofread_d.pdf |
| Mr.Wolf: An Energy-Precision Scalable Parallel Ultra Low Power SoC for IoT Edge Processing | Pullini A.; Rossi D.; Loi I.; Tagliavini G.; Benini L. | 2019-01-01 | IEEE JOURNAL OF SOLID-STATE CIRCUITS | - | 1.01 Articolo in rivista | WOLF.pdf |
| A Heterogeneous Multi-Core System-on-Chip for Energy Efficient Brain Inspired Computing | Pullini, Antonio; Conti, Francesco; Rossi, Davide; Loi, Igor; Gautschi, Michael; Benini, Luca | 2018-01-01 | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. II, EXPRESS BRIEFS | - | 1.01 Articolo in rivista | tcas2_resubmit_v5_disclaimer.pdf |
| GAP-8: A RISC-V SoC for AI at the Edge of the IoT | E. Flamand; D. Rossi; F. Conti; I. Loi; A. Pullini; F. Rotenberg; L. Benini | 2018-01-01 | - | - | 4.01 Contributo in Atti di convegno | - |
| Mr. Wolf: A 1 GFLOP/s Energy-Proportional Parallel Ultra Low Power SoC for IOT Edge Processing | Pullini, Antonio; Rossi, Davide; Loi, Igor; Di Mauro, Alfio; Benini, Luca | 2018-01-01 | - | Institute of Electrical and Electronics Engineers Inc. | 4.01 Contributo in Atti di convegno | - |
| Neurostream: Scalable and Energy Efficient Deep Learning with Smart Memory Cubes | Azarkhish, Erfan*; Rossi, Davide; Loi, Igor; Benini, Luca | 2018-01-01 | IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS | - | 1.01 Articolo in rivista | Neurostream_fulltext.pdf |
| Sub-mW multi-Gbps chip-to-chip communication Links for Ultra-Low Power IoT end-nodes | Martino, Dazzi; Pierpaolo, Palestri; Davide, Rossi; Andrea, Bandizioly; Igor, Loi; David, Bellasi...; Luca, Benini | 2018-01-01 | - | - | 4.01 Contributo in Atti di convegno | - |
| The Quest for Energy-Efficient I$ Design in Ultra-Low-Power Clustered Many-Cores | Loi, Igor; Capotondi, Alessandro; Rossi, Davide; Marongiu, Andrea; Benini, Luca | 2018-01-01 | IEEE TRANSACTIONS ON MULTI-SCALE COMPUTING SYSTEMS | - | 1.01 Articolo in rivista | capotondi_TMSCS18.pdf |
| A Hybrid Instruction Prefetching Mechanism for Ultra Low-Power Multicore Clusters | Payami, Maryam*; Azarkhish, Erfan; Loi, Igor; Benini, Luca | 2017-01-01 | IEEE EMBEDDED SYSTEMS LETTERS | - | 1.01 Articolo in rivista | A Hybrid Instruction Prefetching Mechanism_fulltext.pdf |
| A Self-Aware Architecture for PVT Compensation and Power Nap in Near Threshold Processors | Rossi, Davide; Loi, Igor; Pullini, Antonio; Muller, Christoph; Burg, Andreas; Conti, Francesco; B...enini, Luca; Flatresse, Philippe | 2017-01-01 | IEEE DESIGN & TEST | - | 1.01 Articolo in rivista | - |
| An IoT Endpoint System-on-Chip for Secure and Energy-Efficient Near-Sensor Analytics | Conti, Francesco; Schilling, Robert; Schiavone, Pasquale Davide; Pullini, Antonio; Rossi, Davide;... Gurkaynak, Frank Kagan; Muehlberghuber, Michael; Gautschi, Michael; Loi, Igor; Haugou, Germain; Mangard, Stefan; Benini, Luca | 2017-01-01 | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. I, REGULAR PAPERS | - | 1.01 Articolo in rivista | Conti_et_al_2017_postprint.pdf |
| Energy-Efficient Near-Threshold Parallel Computing: The PULPv2 Cluster | Rossi, Davide; Pullini, Antonio; Loi, Igor; Gautschi, Michael; Gurkaynak, Frank Kagan; Teman, Ada...m; Constantin, Jeremy; Burg, Andreas; Miro-Panades, Ivan; Beigne, Edith; Clermidy, Fabien; Flatresse, Philippe; Benini, Luca | 2017-01-01 | IEEE MICRO | - | 1.01 Articolo in rivista | - |
| Logic-Base Interconnect Design for Near Memory Computing in the Smart Memory Cube | Azarkhish, Erfan; Pfister, Christoph; Rossi, Davide; Loi, Igor; Benini, Luca | 2017-01-01 | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | - | 1.01 Articolo in rivista | - |
| Near-Threshold RISC-V Core With DSP Extensions for Scalable IoT Endpoint Devices | Gautschi, Michael; Schiavone, Pasquale Davide; Traber, Andreas; Loi, Igor; Pullini, Antonio; Ross...i, Davide; Flamand, Eric; Gurkaynak, Frank K.; Benini, Luca | 2017-01-01 | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | - | 1.01 Articolo in rivista | GAUTSCHI_TVLSI_2017_disclaimer.pdf |
| Ultra-Low-Power Digital Architectures for the Internet of Things | Rossi, Davide; Loi, Igor; Pullini, Antonio; Benini, Luca | 2017-01-01 | - | Springer International Publishing | 2.01 Capitolo / saggio in libro | - |
| 193 MOPS/mW @ 162 MOPS, 0.32V to 1.15V voltage range multi-core accelerator for energy efficient parallel and sequential digital processing | Rossi, Davide; Pullini, Antonio; Loi, Igor; Gautschi, Michael; Gurkaynak, Frank Kagan; Teman, Ada...m; Constantin, Jeremy; Burg, Andreas; Miro-Panades, Ivan; Beign, Edith; Clermidy, Fabien; Abouzeid, Fady; Flatresse, Philippe; Benini, Luca | 2016-01-01 | - | Institute of Electrical and Electronics Engineers Inc. | 4.01 Contributo in Atti di convegno | - |
| A 60 GOPS/W, -1.8 v to 0.9 v body bias ULP cluster in 28 nm UTBB FD-SOI technology | Rossi, Davide; Pullini, Antonio; Loi, Igor; Gautschi, Michael; Gürkaynak, Frank K.; Bartolini, An...drea; Flatresse, Philippe; Benini, Luca | 2016-01-01 | SOLID-STATE ELECTRONICS | - | 1.01 Articolo in rivista | - |
| A heterogeneous multi-core system-on-chip for energy efficient brain inspired vision | Pullini, Antonio; Conti, Francesco; Rossi, Davide; Loi, Igor; Gautschi, Michael; Benini, Luca | 2016-01-01 | - | Institute of Electrical and Electronics Engineers Inc. | 4.01 Contributo in Atti di convegno | - |
| Curbing the roofline: a scalable and flexible architecture for CNNs on FPGA | Meloni, Paolo; Deriu, Gianfranco; Conti, Francesco; Loi, Igor; Raffo, Luigi; Benini, Luca | 2016-01-01 | - | ACM | 4.01 Contributo in Atti di convegno | - |
| Design and evaluation of a processing-in-memory architecture for the smart memory cube | Azarkhish, Erfan; Rossi, Davide; Loi, Igor; Benini, Luca | 2016-01-01 | - | Springer Verlag | 4.01 Contributo in Atti di convegno | - |