LOI, IGOR
LOI, IGOR
DIPARTIMENTO DI INGEGNERIA DELL'ENERGIA ELETTRICA E DELL'INFORMAZIONE "GUGLIELMO MARCONI"
Collaboratori
Igor L.; Loi I.; I. LOI; Igor Loi
193 MOPS/mW @ 162 MOPS, 0.32V to 1.15V voltage range multi-core accelerator for energy efficient parallel and sequential digital processing
2016 Rossi, Davide; Pullini, Antonio; Loi, Igor; Gautschi, Michael; Gurkaynak, Frank Kagan; Teman, Adam; Constantin, Jeremy; Burg, Andreas; Miro-Panades, Ivan; Beign, Edith; Clermidy, Fabien; Abouzeid, Fady; Flatresse, Philippe; Benini, Luca
3D logarithmic interconnect: Stacking multiple L1 memory dies over multi-core clusters2013 Seventh IEEE/ACM International Symposium on Networks-on-Chip (NoCS)
2013 Erfan Azarkhish;Igor Loi;Luca Benini
3D NoCs — Unifying inter & intra chip communication
2010 Loi I. ; Marchal P. ; Pullini A. ; Benini L.
3D-LIN: A Configurable Low-Latency Interconnect for Multi-Core Clusters with 3D Stacked L1 Memory
2012 G. Beanato; I. Loi; G. De Micheli; Y. Leblebici; L. Benini
4.4 A 1.3TOPS/W @ 32GOPS Fully Integrated 10-Core SoC for IoT End-Nodes with 1.7μW Cognitive Wake-Up from MRAM-Based State-Retentive Sleep Mode
2021 Rossi D.; Conti F.; Eggiman M.; Mach S.; Mauro A.D.; Guermandi M.; Tagliavini G.; Pullini A.; Loi I.; Chen J.; Flamand E.; Benini L.
A -1.8V to 0.9V body bias, 60 GOPS/W 4-core cluster in low-power 28nm UTBB FD-SOI technology
2015 Rossi, Davide; Pullini, Antonio; Gautschi, Michael; Loi, Igor; Gurkaynak, Frank Kagan; Flatresse, Philippe; Benini, Luca
A 60 GOPS/W, -1.8 v to 0.9 v body bias ULP cluster in 28 nm UTBB FD-SOI technology
2016 Rossi, Davide; Pullini, Antonio; Loi, Igor; Gautschi, Michael; Gürkaynak, Frank K.; Bartolini, Andrea; Flatresse, Philippe; Benini, Luca
A case for three-dimensional stacking of tightly coupled data memories over multi-core clusters using low-latency interconnects
2013 Erfan Azarkhish;Luca Benini;Igor Loi
A fully-synthesizable single-cycle interconnection network for Shared-L1 processor clusters
2011 Rahimi A. ; Loi I. ; Kakoee M.R. ; Benini L.
A Heterogeneous Multi-Core System-on-Chip for Energy Efficient Brain Inspired Computing
2018 Pullini, Antonio; Conti, Francesco; Rossi, Davide; Loi, Igor; Gautschi, Michael; Benini, Luca
A heterogeneous multi-core system-on-chip for energy efficient brain inspired vision
2016 Pullini, Antonio; Conti, Francesco; Rossi, Davide; Loi, Igor; Gautschi, Michael; Benini, Luca
A high-performance multiported L2 memory IP for scalable three-dimensional integration2013 IEEE International 3D Systems Integration Conference (3DIC)
2013 Erfan Azarkhish;Igor Loi;Luca Benini
A Hybrid Instruction Prefetching Mechanism for Ultra Low-Power Multicore Clusters
2017 Payami, Maryam*; Azarkhish, Erfan; Loi, Igor; Benini, Luca
A low-overhead fault tolerance scheme for TSV-based 3D network on chip links.
2008 Loi I.; Mitra S.; Lee T.H.; Fujita S.; Benini L.
A Modular Shared L2 Memory Design for 3-D Integration
2015 Azarkhish, Erfan; Rossi, Davide; Loi, Igor; Benini, Luca
A multi banked - Multi ported - Non blocking shared L2 cache for MPSoC platforms
2014 Loi, Igor; Benini, Luca
A new physical routing approach for robust bundled signaling on NoC links
2010 M. R. Kakoee; I. Loi; L. Benini
A resilient architecture for low latency communication in shared-L1 processor clusters
2012 Kakoee M.R.; Loi I. ; Benini L.
A Self-Aware Architecture for PVT Compensation and Power Nap in Near Threshold Processors
2017 Rossi, Davide; Loi, Igor; Pullini, Antonio; Muller, Christoph; Burg, Andreas; Conti, Francesco; Benini, Luca; Flatresse, Philippe
A shared-FPU architecture for ultra-low power MPSoCs, Proceedings of the ACM International Conference on Computing Frontiers - CF '13
2013 Mohammad Reza Kakoee;Igor Loi;Luca Benini
Titolo | Autore(i) | Anno | Periodico | Editore | Tipo | File |
---|---|---|---|---|---|---|
193 MOPS/mW @ 162 MOPS, 0.32V to 1.15V voltage range multi-core accelerator for energy efficient parallel and sequential digital processing | Rossi, Davide; Pullini, Antonio; Loi, Igor; Gautschi, Michael; Gurkaynak, Frank Kagan; Teman, Ada...m; Constantin, Jeremy; Burg, Andreas; Miro-Panades, Ivan; Beign, Edith; Clermidy, Fabien; Abouzeid, Fady; Flatresse, Philippe; Benini, Luca | 2016-01-01 | - | Institute of Electrical and Electronics Engineers Inc. | 4.01 Contributo in Atti di convegno | - |
3D logarithmic interconnect: Stacking multiple L1 memory dies over multi-core clusters2013 Seventh IEEE/ACM International Symposium on Networks-on-Chip (NoCS) | Erfan Azarkhish;Igor Loi;Luca Benini | 2013-01-01 | - | IEEE | 4.01 Contributo in Atti di convegno | - |
3D NoCs — Unifying inter & intra chip communication | Loi I. ; Marchal P. ; Pullini A. ; Benini L. | 2010-01-01 | - | IEEE Press | 4.01 Contributo in Atti di convegno | - |
3D-LIN: A Configurable Low-Latency Interconnect for Multi-Core Clusters with 3D Stacked L1 Memory | G. Beanato; I. Loi; G. De Micheli; Y. Leblebici; L. Benini | 2012-01-01 | - | IEEE Press | 4.01 Contributo in Atti di convegno | - |
4.4 A 1.3TOPS/W @ 32GOPS Fully Integrated 10-Core SoC for IoT End-Nodes with 1.7μW Cognitive Wake-Up from MRAM-Based State-Retentive Sleep Mode | Rossi D.; Conti F.; Eggiman M.; Mach S.; Mauro A.D.; Guermandi M.; Tagliavini G.; Pullini A.; Loi... I.; Chen J.; Flamand E.; Benini L. | 2021-01-01 | - | Institute of Electrical and Electronics Engineers Inc. | 4.01 Contributo in Atti di convegno | 09365939.pdf; paper_proofread_d.pdf |
A -1.8V to 0.9V body bias, 60 GOPS/W 4-core cluster in low-power 28nm UTBB FD-SOI technology | Rossi, Davide; Pullini, Antonio; Gautschi, Michael; Loi, Igor; Gurkaynak, Frank Kagan; Flatresse,... Philippe; Benini, Luca | 2015-01-01 | - | Institute of Electrical and Electronics Engineers Inc. | 4.01 Contributo in Atti di convegno | A −1.8V to 0.9V body bias, 60 GOPS-W 4-core cluster in low-power 28nm UTBB FD-SOI technology.pdf; A -1.8V to 0.9V Body Bias_Postprint..pdf |
A 60 GOPS/W, -1.8 v to 0.9 v body bias ULP cluster in 28 nm UTBB FD-SOI technology | Rossi, Davide; Pullini, Antonio; Loi, Igor; Gautschi, Michael; Gürkaynak, Frank K.; Bartolini, An...drea; Flatresse, Philippe; Benini, Luca | 2016-01-01 | SOLID-STATE ELECTRONICS | - | 1.01 Articolo in rivista | - |
A case for three-dimensional stacking of tightly coupled data memories over multi-core clusters using low-latency interconnects | Erfan Azarkhish;Luca Benini;Igor Loi | 2013-01-01 | IET COMPUTERS & DIGITAL TECHNIQUES | - | 1.01 Articolo in rivista | - |
A fully-synthesizable single-cycle interconnection network for Shared-L1 processor clusters | Rahimi A. ; Loi I. ; Kakoee M.R. ; Benini L. | 2011-01-01 | - | IEEE Press | 4.01 Contributo in Atti di convegno | - |
A Heterogeneous Multi-Core System-on-Chip for Energy Efficient Brain Inspired Computing | Pullini, Antonio; Conti, Francesco; Rossi, Davide; Loi, Igor; Gautschi, Michael; Benini, Luca | 2018-01-01 | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. II, EXPRESS BRIEFS | - | 1.01 Articolo in rivista | tcas2_resubmit_v5_disclaimer.pdf |
A heterogeneous multi-core system-on-chip for energy efficient brain inspired vision | Pullini, Antonio; Conti, Francesco; Rossi, Davide; Loi, Igor; Gautschi, Michael; Benini, Luca | 2016-01-01 | - | Institute of Electrical and Electronics Engineers Inc. | 4.01 Contributo in Atti di convegno | - |
A high-performance multiported L2 memory IP for scalable three-dimensional integration2013 IEEE International 3D Systems Integration Conference (3DIC) | Erfan Azarkhish;Igor Loi;Luca Benini | 2013-01-01 | - | 2013 IEEE Conference Proceedings | 4.01 Contributo in Atti di convegno | - |
A Hybrid Instruction Prefetching Mechanism for Ultra Low-Power Multicore Clusters | Payami, Maryam*; Azarkhish, Erfan; Loi, Igor; Benini, Luca | 2017-01-01 | IEEE EMBEDDED SYSTEMS LETTERS | - | 1.01 Articolo in rivista | A Hybrid Instruction Prefetching Mechanism_fulltext.pdf |
A low-overhead fault tolerance scheme for TSV-based 3D network on chip links. | Loi I.; Mitra S.; Lee T.H.; Fujita S.; Benini L. | 2008-01-01 | - | IEEE | 4.01 Contributo in Atti di convegno | - |
A Modular Shared L2 Memory Design for 3-D Integration | Azarkhish, Erfan; Rossi, Davide; Loi, Igor; Benini, Luca | 2015-01-01 | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | - | 1.01 Articolo in rivista | - |
A multi banked - Multi ported - Non blocking shared L2 cache for MPSoC platforms | Loi, Igor; Benini, Luca | 2014-01-01 | PROCEEDINGS - DESIGN, AUTOMATION, AND TEST IN EUROPE CONFERENCE AND EXHIBITION | Institute of Electrical and Electronics Engineers Inc. | 4.01 Contributo in Atti di convegno | - |
A new physical routing approach for robust bundled signaling on NoC links | M. R. Kakoee; I. Loi; L. Benini | 2010-01-01 | - | ACM | 4.01 Contributo in Atti di convegno | - |
A resilient architecture for low latency communication in shared-L1 processor clusters | Kakoee M.R.; Loi I. ; Benini L. | 2012-01-01 | - | IEEE Press | 4.01 Contributo in Atti di convegno | - |
A Self-Aware Architecture for PVT Compensation and Power Nap in Near Threshold Processors | Rossi, Davide; Loi, Igor; Pullini, Antonio; Muller, Christoph; Burg, Andreas; Conti, Francesco; B...enini, Luca; Flatresse, Philippe | 2017-01-01 | IEEE DESIGN & TEST | - | 1.01 Articolo in rivista | - |
A shared-FPU architecture for ultra-low power MPSoCs, Proceedings of the ACM International Conference on Computing Frontiers - CF '13 | Mohammad Reza Kakoee;Igor Loi;Luca Benini | 2013-01-01 | - | - | 4.01 Contributo in Atti di convegno | - |