3D integration of solid-state memories and logic, as demonstrated by the Hybrid Memory Cube (HMC), offers major opportunities for revisiting near-memory computation and gives new hope to mitigate the power and performance losses caused by the “memory wall”. Several publications in the past few years demonstrate this renewed interest. In this paper we present the first exploration steps towards design of the Smart Memory Cube (SMC), a new Processor-in-Memory (PIM) architecture that enhances the capabilities of the logic-base (LoB) die in HMC. An accurate simulation environment called SMCSim has been developed, along with a full featured software stack. The key contribution of this work is full system analysis of near memory computation including high-level software to low-level firmware and hardware layers, considering offloading and dynamic overheads caused by the operating system (OS), cache coherence, and memory management. A zero-copy pointer passing mechanism has been devised to allow low overhead data sharing between the host and the PIM. Benchmarking results demonstrate up to 2X performance improvement in comparison with the host Systemon-Chip (SoC), and around 1.5X against a similar host-side accelerator. Moreover, by scaling down the voltage and frequency of PIM’s processor it is possible to reduce energy by around 70% and 55% in comparison with the host and the accelerator, respectively.

Design and evaluation of a processing-in-memory architecture for the smart memory cube / Azarkhish, Erfan; Rossi, Davide; Loi, Igor; Benini, Luca. - STAMPA. - 9637:(2016), pp. 19-31. (Intervento presentato al convegno 29th International Conference on Architecture of Computing Systems, ARCS 2016 tenutosi a deu nel 2016) [10.1007/978-3-319-30695-7_2].

Design and evaluation of a processing-in-memory architecture for the smart memory cube

AZARKHISH, ERFAN;ROSSI, DAVIDE;LOI, IGOR;BENINI, LUCA
2016

Abstract

3D integration of solid-state memories and logic, as demonstrated by the Hybrid Memory Cube (HMC), offers major opportunities for revisiting near-memory computation and gives new hope to mitigate the power and performance losses caused by the “memory wall”. Several publications in the past few years demonstrate this renewed interest. In this paper we present the first exploration steps towards design of the Smart Memory Cube (SMC), a new Processor-in-Memory (PIM) architecture that enhances the capabilities of the logic-base (LoB) die in HMC. An accurate simulation environment called SMCSim has been developed, along with a full featured software stack. The key contribution of this work is full system analysis of near memory computation including high-level software to low-level firmware and hardware layers, considering offloading and dynamic overheads caused by the operating system (OS), cache coherence, and memory management. A zero-copy pointer passing mechanism has been devised to allow low overhead data sharing between the host and the PIM. Benchmarking results demonstrate up to 2X performance improvement in comparison with the host Systemon-Chip (SoC), and around 1.5X against a similar host-side accelerator. Moreover, by scaling down the voltage and frequency of PIM’s processor it is possible to reduce energy by around 70% and 55% in comparison with the host and the accelerator, respectively.
2016
Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
19
31
Design and evaluation of a processing-in-memory architecture for the smart memory cube / Azarkhish, Erfan; Rossi, Davide; Loi, Igor; Benini, Luca. - STAMPA. - 9637:(2016), pp. 19-31. (Intervento presentato al convegno 29th International Conference on Architecture of Computing Systems, ARCS 2016 tenutosi a deu nel 2016) [10.1007/978-3-319-30695-7_2].
Azarkhish, Erfan; Rossi, Davide; Loi, Igor; Benini, Luca
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11585/572056
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