ROSSI, DAVIDE
ROSSI, DAVIDE
DIPARTIMENTO DI INGEGNERIA DELL'ENERGIA ELETTRICA E DELL'INFORMAZIONE "GUGLIELMO MARCONI"
Docenti di ruolo di IIa fascia
A 0.5GHz 0.35mW LDO-Powered Constant-Slope Phase Interpolator with 0.22% INL
2021-01-01 Elnaqib A.; Okuhara H.; Jang T.; Rossi D.; Benini L.
A 1.15 TOPS/W, 16-Cores Parallel Ultra-Low Power Cluster with 2b-to-32b Fully Flexible Bit-Precision and Vector Lockstep Execution Mode
2021-01-01 Garofalo A.; Ottavi G.; Di Mauro A.; Conti F.; Tagliavini G.; Benini L.; Rossi D.
A -1.8V to 0.9V body bias, 60 GOPS/W 4-core cluster in low-power 28nm UTBB FD-SOI technology
2015-01-01 Rossi, Davide; Pullini, Antonio; Gautschi, Michael; Loi, Igor; Gurkaynak, Frank Kagan; Flatresse, Philippe; Benini, Luca
A 142MOPS/mW integrated programmable array accelerator for smart visual processing
2017-01-01 Das, Satyajit; Rossi, Davide; Martin Kevin, J. M.; Coussy, Philippe; Benini, Luca
193 MOPS/mW @ 162 MOPS, 0.32V to 1.15V voltage range multi-core accelerator for energy efficient parallel and sequential digital processing
2016-01-01 Rossi, Davide; Pullini, Antonio; Loi, Igor; Gautschi, Michael; Gurkaynak, Frank Kagan; Teman, Adam; Constantin, Jeremy; Burg, Andreas; Miro-Panades, Ivan; Beign, Edith; Clermidy, Fabien; Abouzeid, Fady; Flatresse, Philippe; Benini, Luca
A 2 MS/s 10A Hall current sensor SoC with digital compressive sensing encoder in 0.16 μm BCD
2016-01-01 Crescentini, M.; Biondi, M.; Bennati, M.; Alberti, P.; Luciani, G.; Tamburini, C.; Pizzotti, M.; Romani, A.; Tartagni, M.; Bellasi, D.; Rossi, D.; Benini, L.; Marchesi, M.; Cristaudo, D.; Canegallo, R.
4.4 A 1.3TOPS/W @ 32GOPS Fully Integrated 10-Core SoC for IoT End-Nodes with 1.7μW Cognitive Wake-Up from MRAM-Based State-Retentive Sleep Mode
2021-01-01 Rossi D.; Conti F.; Eggiman M.; Mach S.; Mauro A.D.; Guermandi M.; Tagliavini G.; Pullini A.; Loi I.; Chen J.; Flamand E.; Benini L.
A 60 GOPS/W, -1.8 v to 0.9 v body bias ULP cluster in 28 nm UTBB FD-SOI technology
2016-01-01 Rossi, Davide; Pullini, Antonio; Loi, Igor; Gautschi, Michael; Gürkaynak, Frank K.; Bartolini, Andrea; Flatresse, Philippe; Benini, Luca
A coarse-grain reconfigurable architecture for multimedia applications supporting subword and floating-point calculations
2010-01-01 C.Brunelli; F.Garzia; D.Rossi; J.Nurmi
A FPGA Implementation of An Open-Source Floating-Point Computation System
2005-01-01 C. Brunelli; F. Garzia; J. Nurmi C. Mucci; F. Campi; D. Rossi
A Fully Programmable eFPGA-Augmented SoC for Smart Power Applications
2020-01-01 Renzini, Francesco; Mucci, Claudio; Rossi, Davide; Franchi Scarselli, Eleonora; Canegallo, Roberto
A Heterogeneous Digital Signal Processor for Dynamically Reconfigurable Computing
2010-01-01 D. Rossi; F. Campi; S. Spolzino; S. Pucillo; R. Guerrieri
A Heterogeneous Digital Signal Processor Implementation for Dynamically Reconfigurable Computing
2009-01-01 D.Rossi; F.Campi; A.Deledda; S.Spolzino; S.Pucillo
A Multi-Core Signal Processor for Heterogeneous Reconfigurable Computing
2009-01-01 D. Rossi; F. Campi; A. Deledda; C. Mucci; S. Pucillo; S. Whitty; R. Ernst; S. Chevobbe; S. Guyetant; M. Kühnle; M. Hübner; J. Becker; W. Putzke-Roeming
A variation tolerant architecture for ultra low power multi-processor cluster
2013-01-01 Daniele Bortolotti;Davide Rossi;Andrea Bartolini;Luca Benini
A VHDL model and Implementation of a Coarse-Grain Reconfigurable Coprocessor for a RISC Core
2006-01-01 C. Brunelli; F. Cinelli; D. Rossi; J. Nurmi
Always-On 674μW@4GOP/s Error Resilient Binary Neural Networks With Aggressive SRAM Voltage Scaling on a 22-nm IoT End-Node
2020-01-01 Alfio Di Mauro, Francesco Conti, Pasquale Davide Schiavone, Davide Rossi, Luca Benini
Always-on motion detection with application-level error control on a near-threshold approximate computing platform
2016-01-01 Tagliavini, Giuseppe; Marongiu, Andrea; Rossi, Davide; Benini, Luca
Always-ON visual node with a hardware-software event-based binarized neural network inference engine
2018-01-01 Rusci, Manuele; Rossi, Davide; Flamand, Eric; Gottardi, Massimo; Farella, Elisabetta; Benini, Luca
Analytical modeling of jitter in bang-bang CDR circuits featuring phase interpolation
2021-01-01 Palestri P.; Elnaqib A.; Menin D.; Shyti K.; Brandonisio F.; Bandiziol A.; Rossi D.; Nonis R.
| Titolo | Autore(i) | Anno | Periodico | Editore | Tipo | File |
|---|---|---|---|---|---|---|
| A 0.5GHz 0.35mW LDO-Powered Constant-Slope Phase Interpolator with 0.22% INL | Elnaqib A.; Okuhara H.; Jang T.; Rossi D.; Benini L. | 2021-01-01 | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. II, EXPRESS BRIEFS | - | 1.01 Articolo in rivista | A 0.5GHz 0.35mW.pdf; A 0.5GHz 0.35mW_Pprint.pdf |
| A 1.15 TOPS/W, 16-Cores Parallel Ultra-Low Power Cluster with 2b-to-32b Fully Flexible Bit-Precision and Vector Lockstep Execution Mode | Garofalo A.; Ottavi G.; Di Mauro A.; Conti F.; Tagliavini G.; Benini L.; Rossi D. | 2021-01-01 | - | Institute of Electrical and Electronics Engineers Inc. | 4.01 Contributo in Atti di convegno | DUSTIN_REDUX.pdf |
| A -1.8V to 0.9V body bias, 60 GOPS/W 4-core cluster in low-power 28nm UTBB FD-SOI technology | Rossi, Davide; Pullini, Antonio; Gautschi, Michael; Loi, Igor; Gurkaynak, Frank Kagan; Flatresse,... Philippe; Benini, Luca | 2015-01-01 | - | Institute of Electrical and Electronics Engineers Inc. | 4.01 Contributo in Atti di convegno | A −1.8V to 0.9V body bias, 60 GOPS-W 4-core cluster in low-power 28nm UTBB FD-SOI technology.pdf; A -1.8V to 0.9V Body Bias_Postprint..pdf |
| A 142MOPS/mW integrated programmable array accelerator for smart visual processing | Das, Satyajit; Rossi, Davide; Martin Kevin, J. M.; Coussy, Philippe; Benini, Luca | 2017-01-01 | - | IEEE | 4.01 Contributo in Atti di convegno | - |
| 193 MOPS/mW @ 162 MOPS, 0.32V to 1.15V voltage range multi-core accelerator for energy efficient parallel and sequential digital processing | Rossi, Davide; Pullini, Antonio; Loi, Igor; Gautschi, Michael; Gurkaynak, Frank Kagan; Teman, Ada...m; Constantin, Jeremy; Burg, Andreas; Miro-Panades, Ivan; Beign, Edith; Clermidy, Fabien; Abouzeid, Fady; Flatresse, Philippe; Benini, Luca | 2016-01-01 | - | Institute of Electrical and Electronics Engineers Inc. | 4.01 Contributo in Atti di convegno | - |
| A 2 MS/s 10A Hall current sensor SoC with digital compressive sensing encoder in 0.16 μm BCD | Crescentini, M.; Biondi, M.; Bennati, M.; Alberti, P.; Luciani, G.; Tamburini, C.; Pizzotti, M.; ...Romani, A.; Tartagni, M.; Bellasi, D.; Rossi, D.; Benini, L.; Marchesi, M.; Cristaudo, D.; Canegallo, R. | 2016-01-01 | - | IEEE | 4.01 Contributo in Atti di convegno | - |
| 4.4 A 1.3TOPS/W @ 32GOPS Fully Integrated 10-Core SoC for IoT End-Nodes with 1.7μW Cognitive Wake-Up from MRAM-Based State-Retentive Sleep Mode | Rossi D.; Conti F.; Eggiman M.; Mach S.; Mauro A.D.; Guermandi M.; Tagliavini G.; Pullini A.; Loi... I.; Chen J.; Flamand E.; Benini L. | 2021-01-01 | - | Institute of Electrical and Electronics Engineers Inc. | 4.01 Contributo in Atti di convegno | 09365939.pdf; paper_proofread_d.pdf |
| A 60 GOPS/W, -1.8 v to 0.9 v body bias ULP cluster in 28 nm UTBB FD-SOI technology | Rossi, Davide; Pullini, Antonio; Loi, Igor; Gautschi, Michael; Gürkaynak, Frank K.; Bartolini, An...drea; Flatresse, Philippe; Benini, Luca | 2016-01-01 | SOLID-STATE ELECTRONICS | - | 1.01 Articolo in rivista | - |
| A coarse-grain reconfigurable architecture for multimedia applications supporting subword and floating-point calculations | C.Brunelli; F.Garzia; D.Rossi; J.Nurmi | 2010-01-01 | JOURNAL OF SYSTEMS ARCHITECTURE | - | 1.01 Articolo in rivista | - |
| A FPGA Implementation of An Open-Source Floating-Point Computation System | C. Brunelli; F. Garzia; J. Nurmi C. Mucci; F. Campi; D. Rossi | 2005-01-01 | - | s.n | 4.01 Contributo in Atti di convegno | - |
| A Fully Programmable eFPGA-Augmented SoC for Smart Power Applications | Renzini, Francesco; Mucci, Claudio; Rossi, Davide; Franchi Scarselli, Eleonora; Canegallo, Roberto | 2020-01-01 | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. I, REGULAR PAPERS | - | 1.01 Articolo in rivista | intero_no_format.pdf |
| A Heterogeneous Digital Signal Processor for Dynamically Reconfigurable Computing | D. Rossi; F. Campi; S. Spolzino; S. Pucillo; R. Guerrieri | 2010-01-01 | IEEE JOURNAL OF SOLID-STATE CIRCUITS | - | 1.01 Articolo in rivista | - |
| A Heterogeneous Digital Signal Processor Implementation for Dynamically Reconfigurable Computing | D.Rossi; F.Campi; A.Deledda; S.Spolzino; S.Pucillo | 2009-01-01 | - | IEEE | 4.01 Contributo in Atti di convegno | - |
| A Multi-Core Signal Processor for Heterogeneous Reconfigurable Computing | D. Rossi; F. Campi; A. Deledda; C. Mucci; S. Pucillo; S. Whitty; R. Ernst; S. Chevobbe; S. Guyeta...nt; M. Kühnle; M. Hübner; J. Becker; W. Putzke-Roeming | 2009-01-01 | - | IEEE | 4.01 Contributo in Atti di convegno | - |
| A variation tolerant architecture for ultra low power multi-processor cluster | Daniele Bortolotti;Davide Rossi;Andrea Bartolini;Luca Benini | 2013-01-01 | - | 2013 IEEE | 4.01 Contributo in Atti di convegno | - |
| A VHDL model and Implementation of a Coarse-Grain Reconfigurable Coprocessor for a RISC Core | C. Brunelli; F. Cinelli; D. Rossi; J. Nurmi | 2006-01-01 | - | s.n | 4.01 Contributo in Atti di convegno | - |
| Always-On 674μW@4GOP/s Error Resilient Binary Neural Networks With Aggressive SRAM Voltage Scaling on a 22-nm IoT End-Node | Alfio Di Mauro, Francesco Conti, Pasquale Davide Schiavone, Davide Rossi, Luca Benini | 2020-01-01 | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. I, REGULAR PAPERS | - | 1.01 Articolo in rivista | - |
| Always-on motion detection with application-level error control on a near-threshold approximate computing platform | Tagliavini, Giuseppe; Marongiu, Andrea; Rossi, Davide; Benini, Luca | 2016-01-01 | - | Institute of Electrical and Electronics Engineers Inc. | 4.01 Contributo in Atti di convegno | - |
| Always-ON visual node with a hardware-software event-based binarized neural network inference engine | Rusci, Manuele; Rossi, Davide; Flamand, Eric; Gottardi, Massimo; Farella, Elisabetta; Benini, Luca | 2018-01-01 | - | Association for Computing Machinery, Inc | 4.01 Contributo in Atti di convegno | Always-ON Visual node.pdf |
| Analytical modeling of jitter in bang-bang CDR circuits featuring phase interpolation | Palestri P.; Elnaqib A.; Menin D.; Shyti K.; Brandonisio F.; Bandiziol A.; Rossi D.; Nonis R. | 2021-01-01 | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | - | 1.01 Articolo in rivista | - |