Next-generation mixed-criticality Systems-on-chip (SoCs)for robotics, automotive, and space must execute mixed-criticality AI-enhanced sensor processing and control workloads, ensuring reliable and time-predictable execution of critical tasks sharing resources with non-critical tasks, while also fitting within a sub-2W power envelope. To tackle these multi-dimensional challenges,in this brief, we present a 16nm, reliable, time-predictable heterogeneous SoC with multiple programmable accelerators. Within a 1.2W power envelope, the SoC integrates software-configurable hardware IPs to ensure predictable access to shared resources, such as the on-chip interconnect and memory system, leading to tight upper bounds on execution times of critical applications. To accelerate mixed-precision mission-critical AI, the SoC integrates a reliable multi-core accelerator achieving 304.9 GOPS peak performance at 1.6 TOPS/W energy efficiency. Non-critical, compute-intensive, floating-point workloads are accelerated by a dual-core vector cluster, achieving 121.8 GFLOPS at 1.1 TFLOPS/W and 106.8 GFLOPS/mm.

Garofalo, A., Ottaviano, A., Perotti, M., Benz, T., Tortorella, Y., Balas, R., et al. (2025). A Reliable, Time-Predictable Heterogeneous SoC for AI-Enhanced Mixed-Criticality Edge Applications. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. II, EXPRESS BRIEFS, 72(11), 1-1 [10.1109/tcsii.2025.3591225].

A Reliable, Time-Predictable Heterogeneous SoC for AI-Enhanced Mixed-Criticality Edge Applications

Garofalo, Angelo
;
Tortorella, Yvan;Bertaccini, Luca;Ciani, Maicol;Sinigaglia, Mattia;Valente, Luca;Conti, Francesco;Rossi, Davide;Benini, Luca
2025

Abstract

Next-generation mixed-criticality Systems-on-chip (SoCs)for robotics, automotive, and space must execute mixed-criticality AI-enhanced sensor processing and control workloads, ensuring reliable and time-predictable execution of critical tasks sharing resources with non-critical tasks, while also fitting within a sub-2W power envelope. To tackle these multi-dimensional challenges,in this brief, we present a 16nm, reliable, time-predictable heterogeneous SoC with multiple programmable accelerators. Within a 1.2W power envelope, the SoC integrates software-configurable hardware IPs to ensure predictable access to shared resources, such as the on-chip interconnect and memory system, leading to tight upper bounds on execution times of critical applications. To accelerate mixed-precision mission-critical AI, the SoC integrates a reliable multi-core accelerator achieving 304.9 GOPS peak performance at 1.6 TOPS/W energy efficiency. Non-critical, compute-intensive, floating-point workloads are accelerated by a dual-core vector cluster, achieving 121.8 GFLOPS at 1.1 TFLOPS/W and 106.8 GFLOPS/mm.
2025
Garofalo, A., Ottaviano, A., Perotti, M., Benz, T., Tortorella, Y., Balas, R., et al. (2025). A Reliable, Time-Predictable Heterogeneous SoC for AI-Enhanced Mixed-Criticality Edge Applications. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. II, EXPRESS BRIEFS, 72(11), 1-1 [10.1109/tcsii.2025.3591225].
Garofalo, Angelo; Ottaviano, Alessandro; Perotti, Matteo; Benz, Thomas; Tortorella, Yvan; Balas, Robert; Rogenmoser, Michael; Zhang, Chi; Bertaccini, ...espandi
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11585/1025803
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