BERTACCINI, LUCA
BERTACCINI, LUCA
AFORM - AREA FORMAZIONE E DOTTORATO
A Reliable, Time-Predictable Heterogeneous SoC for AI-Enhanced Mixed-Criticality Edge Applications
2025 Garofalo, Angelo; Ottaviano, Alessandro; Perotti, Matteo; Benz, Thomas; Tortorella, Yvan; Balas, Robert; Rogenmoser, Michael; Zhang, Chi; Bertaccini, Luca; Wistoff, Nils; Ciani, Maicol; Koenig, Cyril; Sinigaglia, Mattia; Valente, Luca; Scheffler, Paul; Eggimann, Manuel; Cavalcante, Matheus; Restuccia, Francesco; Biondi, Alessandro; Conti, Francesco; Gurkaynak, Frank K.; Rossi, Davide; Benini, Luca
Maestro: A 302 GFLOPS/W and 19.8GFLOPS RISC-V Vector-Tensor Architecture for Wearable Ultrasound Edge Computing
2025 Sinigaglia, Mattia; Kiamarzi, Amirhossein; Bertuletti, Marco; Ghionda, Luigi; Orlandi, Mattia; Tedeschi, Riccardo; Di Giampietro, Aurora; Tortorella, Yvan; Bertaccini, Luca; Benatti, Simone; Tagliavini, Giuseppe; Benini, Luca; Conti, Francesco; Rossi, Davide
MXDOTP: A RISC-V ISA Extension for Enabling Microscaling (MX) Floating-Point Dot Products
2025 İslamoğlu, Gamze; Bertaccini, Luca; Prasad, Arpan Suravi; Conti, Francesco; Garofalo, Angelo; Benini, Luca
RedMulE-FT: A Reconfigurable Fault-Tolerant Matrix Multiplication Engine
2025 Wiese, Philip; Item, Maurus; Bertaccini, Luca; Tortorella, Yvan; Garofalo, Angelo; Benini, Luca
Extending RISC-V for Efficient Overflow Recovery in Mixed-Precision Computations
2024 Bertaccini, Luca; Shen, Siyuan; Hoefler, Torsten; Benini, Luca
MiniFloats on RISC-V Cores: ISA Extensions With Mixed-Precision Short Dot Products
2024 Bertaccini, L.; Paulin, G.; Cavalcante, M.; Fischer, T.; Mach, S.; Benini, L.
Occamy: A 432-Core 28.1 DP-GFLOP/s/W 83% FPU Utilization Dual-Chiplet, Dual-HBM2E RISC-V-Based Accelerator for Stencil and Sparse Linear Algebra Computations with 8-to-64-bit Floating-Point Support in 12nm FinFET
2024 Paulin, G.; Scheffler, P.; Benz, T.; Cavalcante, M.; Fischer, T.; Eggimann, M.; Zhang, Y.; Wistoff, N.; Bertaccini, L.; Colagrande, L.; Ottavi, G.; Gurkaynak, F. K.; Rossi, D.; Benini, L.
Optimizing Foundation Model Inference on a Many-Tiny-Core Open-Source RISC-V Platform
2024 Potocnik, Viviane; Colagrande, Luca; Fischer, Tim; Bertaccini, Luca; Pagliari, Daniele Jahier; Burrello, Alessio; Benini, Luca
ECHOES: a 200 GOPS/W Frequency Domain SoC with FFT Processor and I2S DSP for Flexible Data Acquisition from Microphone Arrays
2023 Mattia Sinigaglia; Luca Bertaccini; Luca Valente; Angelo Garofalo; Simone Benatti; Luca Benini; Francesco Conti; Davide Rossi
MiniFloat-NN and ExSdotp: An ISA Extension and a Modular Open Hardware Unit for Low-Precision Training on RISC-V Cores
2022 Bertaccini, Luca; Paulin, Gianna; Fischer, Tim; Mach, Stefan; Benini, Luca
Tiny-FPU: Low-cost floating-point support for small RISC-V MCU cores
2021 Bertaccini L.; Perotti M.; Mach S.; Schiavone P.D.; Zaruba F.; Benini L.
| Titolo | Autore(i) | Anno | Periodico | Editore | Tipo | File |
|---|---|---|---|---|---|---|
| A Reliable, Time-Predictable Heterogeneous SoC for AI-Enhanced Mixed-Criticality Edge Applications | Garofalo, Angelo; Ottaviano, Alessandro; Perotti, Matteo; Benz, Thomas; Tortorella, Yvan; Balas, ...Robert; Rogenmoser, Michael; Zhang, Chi; Bertaccini, Luca; Wistoff, Nils; Ciani, Maicol; Koenig, Cyril; Sinigaglia, Mattia; Valente, Luca; Scheffler, Paul; Eggimann, Manuel; Cavalcante, Matheus; Restuccia, Francesco; Biondi, Alessandro; Conti, Francesco; Gurkaynak, Frank K.; Rossi, Davide; Benini, Luca | 2025-01-01 | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. II, EXPRESS BRIEFS | - | 1.01 Articolo in rivista | TCAS-II-24419-2025_final_submission_manuscript.pdf |
| Maestro: A 302 GFLOPS/W and 19.8GFLOPS RISC-V Vector-Tensor Architecture for Wearable Ultrasound Edge Computing | Sinigaglia, Mattia; Kiamarzi, Amirhossein; Bertuletti, Marco; Ghionda, Luigi; Orlandi, Mattia; Te...deschi, Riccardo; Di Giampietro, Aurora; Tortorella, Yvan; Bertaccini, Luca; Benatti, Simone; Tagliavini, Giuseppe; Benini, Luca; Conti, Francesco; Rossi, Davide | 2025-01-01 | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. I, REGULAR PAPERS | - | 1.01 Articolo in rivista | - |
| MXDOTP: A RISC-V ISA Extension for Enabling Microscaling (MX) Floating-Point Dot Products | İslamoğlu, Gamze; Bertaccini, Luca; Prasad, Arpan Suravi; Conti, Francesco; Garofalo, Angelo; Be...nini, Luca | 2025-01-01 | - | Institute of Electrical and Electronics Engineers Inc. | 4.01 Contributo in Atti di convegno | - |
| RedMulE-FT: A Reconfigurable Fault-Tolerant Matrix Multiplication Engine | Wiese, Philip; Item, Maurus; Bertaccini, Luca; Tortorella, Yvan; Garofalo, Angelo; Benini, Luca | 2025-01-01 | - | Association for Computing Machinery, Inc | 4.01 Contributo in Atti di convegno | - |
| Extending RISC-V for Efficient Overflow Recovery in Mixed-Precision Computations | Bertaccini, Luca; Shen, Siyuan; Hoefler, Torsten; Benini, Luca | 2024-01-01 | - | Institute of Electrical and Electronics Engineers Inc. | 4.01 Contributo in Atti di convegno | - |
| MiniFloats on RISC-V Cores: ISA Extensions With Mixed-Precision Short Dot Products | Bertaccini, L.; Paulin, G.; Cavalcante, M.; Fischer, T.; Mach, S.; Benini, L. | 2024-01-01 | IEEE TRANSACTIONS ON EMERGING TOPICS IN COMPUTING | - | 1.01 Articolo in rivista | - |
| Occamy: A 432-Core 28.1 DP-GFLOP/s/W 83% FPU Utilization Dual-Chiplet, Dual-HBM2E RISC-V-Based Accelerator for Stencil and Sparse Linear Algebra Computations with 8-to-64-bit Floating-Point Support in 12nm FinFET | Paulin, G.; Scheffler, P.; Benz, T.; Cavalcante, M.; Fischer, T.; Eggimann, M.; Zhang, Y.; Wistof...f, N.; Bertaccini, L.; Colagrande, L.; Ottavi, G.; Gurkaynak, F. K.; Rossi, D.; Benini, L. | 2024-01-01 | - | Institute of Electrical and Electronics Engineers Inc. | 4.01 Contributo in Atti di convegno | - |
| Optimizing Foundation Model Inference on a Many-Tiny-Core Open-Source RISC-V Platform | Potocnik, Viviane; Colagrande, Luca; Fischer, Tim; Bertaccini, Luca; Pagliari, Daniele Jahier; Bu...rrello, Alessio; Benini, Luca | 2024-01-01 | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR ARTIFICIAL INTELLIGENCE | - | 1.01 Articolo in rivista | - |
| ECHOES: a 200 GOPS/W Frequency Domain SoC with FFT Processor and I2S DSP for Flexible Data Acquisition from Microphone Arrays | Mattia Sinigaglia; Luca Bertaccini; Luca Valente; Angelo Garofalo; Simone Benatti; Luca Benini; F...rancesco Conti; Davide Rossi | 2023-01-01 | IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS PROCEEDINGS | IEEE | 4.01 Contributo in Atti di convegno | - |
| MiniFloat-NN and ExSdotp: An ISA Extension and a Modular Open Hardware Unit for Low-Precision Training on RISC-V Cores | Bertaccini, Luca; Paulin, Gianna; Fischer, Tim; Mach, Stefan; Benini, Luca | 2022-01-01 | - | IEEE COMPUTER SOC | 4.01 Contributo in Atti di convegno | - |
| Tiny-FPU: Low-cost floating-point support for small RISC-V MCU cores | Bertaccini L.; Perotti M.; Mach S.; Schiavone P.D.; Zaruba F.; Benini L. | 2021-01-01 | - | Institute of Electrical and Electronics Engineers Inc. | 4.01 Contributo in Atti di convegno | - |