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EnglishIn the Internet-Of-Things (IoT) domain, microcontrollers (MCUs) are used to collect and process data coming from sensors and transmit them to the cloud. Applications that require the range and precision of floating-point (FP) arithmetic can be implemented using efficient hardware floating-point units (FPUs) or by using software emulation. FPUs optimize performance and code size, whilst software emulation minimizes the hardware cost. We present a new area-optimized, IEEE 754-compliant RISC-V FPU (Tiny-FPU), and we explore the area, code size, performance, power, and energy efficiency of three different implementations of the RISC-V Instruction Set Architecture double and single-precision FP extensions on an MCU-class processor. We show that Tiny-FPU, in its double and single-precision versions, is respectively 54% and 37% smaller than a double and single-precision FPU optimized for performance and energy efficiency. When coupling a RISC-V core with Tiny-FPU, we achieve up to 18.5× and 15.5× speedups with respect to the same core emulating FP operations via software.
| Titolo: | Tiny-FPU: Low-cost floating-point support for small RISC-V MCU cores | |
| Autore/i: | Bertaccini L.; Perotti M.; Mach S.; Schiavone P. D.; Zaruba F.; Benini L. | |
| Autore/i Unibo: | ||
| Anno: | 2021 | |
| Titolo del libro: | Proceedings - IEEE International Symposium on Circuits and Systems | |
| Pagina iniziale: | 1 | |
| Pagina finale: | 5 | |
| Digital Object Identifier (DOI): | http://dx.doi.org/10.1109/ISCAS51556.2021.9401149 | |
| Abstract: | In the Internet-Of-Things (IoT) domain, microcontrollers (MCUs) are used to collect and process data coming from sensors and transmit them to the cloud. Applications that require the range and precision of floating-point (FP) arithmetic can be implemented using efficient hardware floating-point units (FPUs) or by using software emulation. FPUs optimize performance and code size, whilst software emulation minimizes the hardware cost. We present a new area-optimized, IEEE 754-compliant RISC-V FPU (Tiny-FPU), and we explore the area, code size, performance, power, and energy efficiency of three different implementations of the RISC-V Instruction Set Architecture double and single-precision FP extensions on an MCU-class processor. We show that Tiny-FPU, in its double and single-precision versions, is respectively 54% and 37% smaller than a double and single-precision FPU optimized for performance and energy efficiency. When coupling a RISC-V core with Tiny-FPU, we achieve up to 18.5× and 15.5× speedups with respect to the same core emulating FP operations via software. | |
| Data stato definitivo: | 26-feb-2022 | |
| Appare nelle tipologie: | 4.01 Contributo in Atti di convegno |
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