GAROFALO, ANGELO

GAROFALO, ANGELO  

DIPARTIMENTO DI INGEGNERIA DELL'ENERGIA ELETTRICA E DELL'INFORMAZIONE "GUGLIELMO MARCONI"  

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Risultati 1 - 12 di 12 (tempo di esecuzione: 0.018 secondi).
Titolo Autore(i) Anno Periodico Editore Tipo File
A 1.15 TOPS/W, 16-Cores Parallel Ultra-Low Power Cluster with 2b-to-32b Fully Flexible Bit-Precision and Vector Lockstep Execution Mode Garofalo A.; Ottavi G.; Di Mauro A.; Conti F.; Tagliavini G.; Benini L.; Rossi D. 2021-01-01 - Institute of Electrical and Electronics Engineers Inc. 4.01 Contributo in Atti di convegno DUSTIN_REDUX.pdf
DORY: Automatic End-to-End Deployment of Real-World DNNs on Low-Cost IoT MCUs Burrello, Alessio; Garofalo, Angelo; Bruschi, Nazareno; Tagliavini, Giuseppe; Rossi, Davide; Cont...i, Francesco 2021-01-01 IEEE TRANSACTIONS ON COMPUTERS - 1.01 Articolo in rivista 2008.0127pp.pdf
Enabling mixed-precision quantized neural networks in extreme-edge devices Nazareno Bruschi, Angelo Garofalo, Francesco Conti, Giuseppe Tagliavini, Davide Rossi 2020-01-01 - Association for Computing Machinery, Inc 4.01 Contributo in Atti di convegno Enabling_Mixed_Precision_Quantized_Neural_Networks_in_Extreme_Edge_Devices.pdf
A Low-Power Transprecision Floating-Point Cluster for Efficient Near-Sensor Data Analytics Montagna F.; Mach S.; Benatti S.; Garofalo A.; Ottavi G.; Benini L.; Rossi D.; Tagliavini G. 2022-01-01 IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS - 1.01 Articolo in rivista Low-Power_Transprecision_Cluster_pp.pdf
A mixed-precision RISC-V processor for extreme-edge DNN inference Ottavi G.; Garofalo A.; Tagliavini G.; Conti F.; Benini L.; Rossi D. 2020-01-01 - IEEE Computer Society 4.01 Contributo in Atti di convegno ISVLSI_STATUS_BASED.pdf
On-line testing for autonomous systems driven by RISC-V processor design verification Ruospo A.; Cantoro R.; Sanchez E.; Schiavone P.D.; Garofalo A.; Benini L. 2019-01-01 - Institute of Electrical and Electronics Engineers Inc. 4.01 Contributo in Atti di convegno -
PULP-NN: A computing library for quantized neural network inference at the edge on RISC-V based parallel ultra low power clusters Garofalo A.; Rusci M.; Conti F.; Rossi D.; Benini L. 2019-01-01 - Institute of Electrical and Electronics Engineers Inc. 4.01 Contributo in Atti di convegno Postprint_PULP-NN_A Computing Library.pdf
PULP-NN: Accelerating Quantized Neural Networks on Parallel Ultra-Low-Power RISC-V Processors Garofalo A.; Rusci M.; Conti F.; Rossi D.; Benini L. 2020-01-01 PHILOSOPHICAL TRANSACTIONS OF THE ROYAL SOCIETY OF LONDON SERIES A: MATHEMATICAL PHYSICAL AND ENGINEERING SCIENCES - 1.01 Articolo in rivista Binder1.pdf
Streamlining the OpenMP Programming Model on Ultra-Low-Power Multi-core MCUs Montagna, Fabio; Tagliavini, Giuseppe; Rossi, Davide; Garofalo, Angelo; Benini, Luca 2021-01-01 - Springer 4.01 Contributo in Atti di convegno ARCS_2021_OMP_postprint.pdf
Work-in-progress: Dory: Lightweight memory hierarchy management for deep NN inference on iot endnodes Burrello A.; Conti F.; Garofalo A.; Rossi D.; Benini L. 2019-01-01 - Association for Computing Machinery, Inc 4.01 Contributo in Atti di convegno esweek_dory_postprint.pdf
XpulpNN: Accelerating Quantized Neural Networks on RISC-V Processors Through ISA Extensions Garofalo, Angelo; Tagliavini, Giuseppe; Conti, Francesco; Rossi, Davide; Benini, Luca 2020-01-01 - Institute of Electrical and Electronics Engineers Inc. (IEEE) 4.01 Contributo in Atti di convegno -
XpulpNN: Enabling Energy Efficient and Flexible Inference of Quantized Neural Networks on RISC-V Based IoT End Nodes Garofalo A.; Tagliavini G.; Conti F.; Benini L.; Rossi D. 2021-01-01 IEEE TRANSACTIONS ON EMERGING TOPICS IN COMPUTING - 1.01 Articolo in rivista XpulpNN_journal_redux.pdf