Reliable Cyber-Physical Systems (CPSs) must ensure their functionality according to the criticality level of their application, even under Single Event Transients (SETs) and Single Event Upsets (SEUs) caused by ionizing radiations. Dual (DCLS) and Triple Core Lockstep (TCLS) are typical radiation-hardening techniques for processors based on spatial redundancy. However, these approaches can be costly when embedding computing platforms into dependable systems with constrained area and budget requirements. We propose a low-cost fault mitigation technique targeted at SETs called Temporal Lockstep (TL), which combines temporal redundancy and minimal spatial repetition to reduce the area overhead with respect to state-of-the-art solutions. TL was implemented on the open-source Ibex core and synthesized in GF 22 nm technology. The area overhead ranges from 53% to 77%, significantly lower than the over 100% and 200% seen in DCLS and TCLS, respectively. Fault injection simulations show an 82.8% reduction in faulty execution outcomes thanks to Temporal Lockstep.
Tedeschi, R., Nadalini, A., Grillotti, F., De Ambroggi, F., Guidetti, E., Benini, L., et al. (2025). A Low-Cost Fault Tolerance Technique for Microcontroller-Class RISC-V Processors. GEWERBESTRASSE 11, CHAM, CH-6330, SWITZERLAND : Springer Science and Business Media Deutschland GmbH [10.1007/978-3-031-71518-1_3].
A Low-Cost Fault Tolerance Technique for Microcontroller-Class RISC-V Processors
Tedeschi, RiccardoPrimo
;Nadalini, AlessandroSecondo
;Benini, LucaPenultimo
;Rossi, DavideUltimo
2025
Abstract
Reliable Cyber-Physical Systems (CPSs) must ensure their functionality according to the criticality level of their application, even under Single Event Transients (SETs) and Single Event Upsets (SEUs) caused by ionizing radiations. Dual (DCLS) and Triple Core Lockstep (TCLS) are typical radiation-hardening techniques for processors based on spatial redundancy. However, these approaches can be costly when embedding computing platforms into dependable systems with constrained area and budget requirements. We propose a low-cost fault mitigation technique targeted at SETs called Temporal Lockstep (TL), which combines temporal redundancy and minimal spatial repetition to reduce the area overhead with respect to state-of-the-art solutions. TL was implemented on the open-source Ibex core and synthesized in GF 22 nm technology. The area overhead ranges from 53% to 77%, significantly lower than the over 100% and 200% seen in DCLS and TCLS, respectively. Fault injection simulations show an 82.8% reduction in faulty execution outcomes thanks to Temporal Lockstep.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
