The early detection of structural malfunctions requires the installation of real-time monitoring systems ensuring continuous access to the damage-sensitive information; nevertheless, it can generate bottlenecks in terms of bandwidth and storage. Deploying data reduction techniques at the edge is recognized as a proficient solution to reduce the systemfs network traffic. However, the most effective solutions currently employed for the purpose are typically based on memory and power-hungry algorithms, making their embedding on resourceconstrained devices very challenging; this is the case of vibration data reduction based on System Identification (SysId) models. This paper presents PARSY-VDD, a fully optimized PArallel end-to-end software framework based on SYstem identification for Vibration-based Damage Detection, as a suitable solution to perform damage detection at the edge in a time and energyefficient manner, avoiding streaming raw data to the cloud. First, we evaluate the damage detection capabilities of PARSYVDD with two benchmarks: a bridge and a wind turbine blade, showcasing the robustness of the end-to-end approach. Then, we deploy PARSY-VDD on both commercial single-core (STM32 family) and a specific multi-core (GAP9) edge device. We introduce an architecture-agnostic algorithmic optimization for SysId, improving the execution by 90× and reducing the consumption by 85× compared with the state-of-the-art SysId implementation on GAP9. Results show that by utilizing the unique parallel computing capabilities of GAP9, the execution time is 751 μs with the high-performance multi-core solution operating at 370MHz and 0.8V, while the energy consumption is 37 μJ with the low-power solution operating at 240MHz and 0.65V. Compared with other single-core implementations based on STM32 microcontrollers, the GAP9 high-performance configuration is 76× faster, while the low-power configuration is 360× more energy efficient.
Kiamarzi, A., Moallemi, A., Zonzini, F., Brunelli, D., Rossi, D., Tagliavini, G. (2025). Parallelization is All System Identification Needs: End-to-end Vibration Diagnostics on a Multi-Core RISC-V Edge Device. IEEE INTERNET OF THINGS JOURNAL, 12(13), 1-15 [10.1109/jiot.2025.3558365].
Parallelization is All System Identification Needs: End-to-end Vibration Diagnostics on a Multi-Core RISC-V Edge Device
Kiamarzi, Amirhossein
Primo
;Moallemi, Amirhossein;Zonzini, Federica;Brunelli, Davide;Rossi, Davide;Tagliavini, Giuseppe
2025
Abstract
The early detection of structural malfunctions requires the installation of real-time monitoring systems ensuring continuous access to the damage-sensitive information; nevertheless, it can generate bottlenecks in terms of bandwidth and storage. Deploying data reduction techniques at the edge is recognized as a proficient solution to reduce the systemfs network traffic. However, the most effective solutions currently employed for the purpose are typically based on memory and power-hungry algorithms, making their embedding on resourceconstrained devices very challenging; this is the case of vibration data reduction based on System Identification (SysId) models. This paper presents PARSY-VDD, a fully optimized PArallel end-to-end software framework based on SYstem identification for Vibration-based Damage Detection, as a suitable solution to perform damage detection at the edge in a time and energyefficient manner, avoiding streaming raw data to the cloud. First, we evaluate the damage detection capabilities of PARSYVDD with two benchmarks: a bridge and a wind turbine blade, showcasing the robustness of the end-to-end approach. Then, we deploy PARSY-VDD on both commercial single-core (STM32 family) and a specific multi-core (GAP9) edge device. We introduce an architecture-agnostic algorithmic optimization for SysId, improving the execution by 90× and reducing the consumption by 85× compared with the state-of-the-art SysId implementation on GAP9. Results show that by utilizing the unique parallel computing capabilities of GAP9, the execution time is 751 μs with the high-performance multi-core solution operating at 370MHz and 0.8V, while the energy consumption is 37 μJ with the low-power solution operating at 240MHz and 0.65V. Compared with other single-core implementations based on STM32 microcontrollers, the GAP9 high-performance configuration is 76× faster, while the low-power configuration is 360× more energy efficient.File | Dimensione | Formato | |
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Parallelization_is_All_System_Identification_Needs_End-to-end_Vibration_Diagnostics_on_a_Multi-Core_RISC-V_Edge_Device.pdf
embargo fino al 08/04/2027
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