Architectural heterogeneity is a promising solution to overcome the utilization wall and provide Moore's Law-like performance scaling in future SoCs. However, heterogeneous architectures increase the size and complexity of the design space, and significant enhancements are required to tools and methodologies to explore this design space effectively. In this work, we describe an extension to the STMicroelectronics P2012 platform and simulation flow to support tightly-coupled shared memory HW processing elements (HWPE), we propose a methodology for the semi-automatic instantiation of HWPEs from a C program, and we explore several architectural variants on a set of computer vision benchmarks.
He-P2012: Architectural heterogeneity exploration on a scalable many-core platform
CONTI, FRANCESCO;MARONGIU, ANDREA;BENINI, LUCA
2014
Abstract
Architectural heterogeneity is a promising solution to overcome the utilization wall and provide Moore's Law-like performance scaling in future SoCs. However, heterogeneous architectures increase the size and complexity of the design space, and significant enhancements are required to tools and methodologies to explore this design space effectively. In this work, we describe an extension to the STMicroelectronics P2012 platform and simulation flow to support tightly-coupled shared memory HW processing elements (HWPE), we propose a methodology for the semi-automatic instantiation of HWPEs from a C program, and we explore several architectural variants on a set of computer vision benchmarks.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
