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Mostrati risultati da 21 a 40 di 138
Titolo Autore(i) Anno Periodico Editore Tipo File
Are Our Design For Testability Features Fault Secure ? C. Metra; T. M. Mak; M. Omaña 2004-01-01 - G. Gielen, J. Figueras 4.01 Contributo in Atti di convegno -
Proceedings 11th IEEE International On-Line Testing Symposium C. Metra; K. Roy; L. Anghel; M. Nicolaidis 2005-01-01 - IEEE 3.02 Curatela -
20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems R. Aitken; C. Metra; N. Park; H. Ito 2005-01-01 - - 7.12 Attività espositiva:Mostra o Esposizione -
Novel On-Chip Circuit for Jitter Testing in High-Speed PLLs J.M. Cazeaux; M. Omaña; C. Metra 2005-01-01 IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT - 1.01 Articolo in rivista -
Exploiting ECC Redundancy to Minimize Crosstalk Impact D. Rossi; A. K. Nieuwland; A. Katoch; C. Metra 2005-01-01 IEEE DESIGN & TEST OF COMPUTERS - 1.01 Articolo in rivista -
Guest editorial C. Metra; R. Leveugle 2005-01-01 - C. Metra, R. Leveugle 2.04 Breve introduzione -
Proceeding of 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems. R. Aitken; H. Ito; C.Metra; N. Park 2005-01-01 - IEEE 3.02 Curatela -
Journal of Electronic Testing C. Metra ; Regis Leveugle 2005-01-01 - C. Metra , Regis Leveugle 3.02 Curatela -
Welcome M. Nicolaidis; C. Metra; L. Anghel; K. Roy 2005-01-01 - C. metra, K. Roy, L. Anghel and M. Nicolaidis 2.04 Breve introduzione -
Message from the Symposium Chairs R. Aitken; C. Metra; H. Ito; N. Park 2005-01-01 - R. Aitken, H. Ito, C. Metra, N. Park 2.04 Breve introduzione -
Load and Logic Co-Optimization for design of Soft-Error Resistant nanometer CMOS Circuits Y. Dhillon; A. Diril; A. Chatterjee; C. Metra 2005-01-01 - C. Metra, K. Roy, L. Anghel, M. Nicolaidis 4.01 Contributo in Atti di convegno -
The Other Side of the Timing Equation: a Result of Clock Faults M. Omaña; D. Rossi; J. M. Cazeaux; TM. Mak; C. Metra 2005-01-01 - R. Aitken, H. Ito, C. Metra, N. Park 4.01 Contributo in Atti di convegno -
Low Cost and High Speed Embedded Two-Rail Code Checker M. Omaña; D. Rossi; C. Metra 2005-01-01 IEEE TRANSACTIONS ON COMPUTERS - 1.01 Articolo in rivista -
New ECC for Crosstalk Effect Minimization D. Rossi; A. K. Nieuwland; A. Katoch; C. Metra 2005-01-01 IEEE DESIGN & TEST OF COMPUTERS - 1.01 Articolo in rivista -
11th IEEE International On-Line Testing Symposium M. Nicolaidis; L. Anghel; C. Metra; K. Roy 2005-01-01 - - 7.12 Attività espositiva:Mostra o Esposizione -
Multiple Transient Faults in Logic: An Issue for Next Generation ICs? D. Rossi; M. Omaña; F. Toma; C. Metra 2005-01-01 - R. Aitken, H. Ito, C. Metra, N. Park 4.01 Contributo in Atti di convegno -
On the Selection of Unidirectional Error detecting Codes for Self-Checking Circuits' Area Overhead and Performance Optimization M. Omaña; O. Losco; C. Metra; A. Pagni 2005-01-01 - C. Metra, K. Roy, L. Anghel, and M. Nicolaidis 4.01 Contributo in Atti di convegno -
On-Transistor Level Gate Sizing for Increased Robustness to Transient Faults J. M. Cazeaux; D. Rossi; M. Omaña; A. Chatterjee; C. Metra 2005-01-01 - C. Metra, K. Roy, L. Anghel, M. Nicolaidis 4.01 Contributo in Atti di convegno -
Self-Checking Voter for High Speed TMR Systems J. M. Cazeaux; D. Rossi; C. Metra 2005-01-01 JOURNAL OF ELECTRONIC TESTING - 1.01 Articolo in rivista -
Coding Techniques for Low Switching Noise in Fault Tolerant Busses A. K. Nieuwland; A. Katoch; D. Rossi; C. Metra 2005-01-01 - C. Metra, K. Roy, L. Anghel, M. Nicolaidis 4.01 Contributo in Atti di convegno -
Mostrati risultati da 21 a 40 di 138
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