CRIS Current Research Information System

ANGIOLINI, FEDERICO
 Distribuzione geografica
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Continente #
NA - Nord America 3.271
AS - Asia 1.446
EU - Europa 1.349
SA - Sud America 83
AF - Africa 61
OC - Oceania 2
Continente sconosciuto - Info sul continente non disponibili 1
Totale 6.213
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Nazione #
US - Stati Uniti d'America 3.265
CN - Cina 483
GB - Regno Unito 431
SG - Singapore 396
VN - Vietnam 284
DE - Germania 197
UA - Ucraina 192
IT - Italia 139
SE - Svezia 108
HK - Hong Kong 105
RU - Federazione Russa 85
IN - India 78
FR - Francia 60
BR - Brasile 59
IE - Irlanda 49
JP - Giappone 32
ZA - Sudafrica 29
EE - Estonia 26
JO - Giordania 26
FI - Finlandia 20
KR - Corea 19
SC - Seychelles 14
AR - Argentina 11
BE - Belgio 11
CI - Costa d'Avorio 11
NL - Olanda 7
AT - Austria 6
TR - Turchia 6
BG - Bulgaria 5
GR - Grecia 5
TG - Togo 5
EC - Ecuador 4
LB - Libano 4
ID - Indonesia 3
IQ - Iraq 3
MX - Messico 3
UY - Uruguay 3
CA - Canada 2
CO - Colombia 2
ES - Italia 2
NZ - Nuova Zelanda 2
PE - Perù 2
RO - Romania 2
RS - Serbia 2
UZ - Uzbekistan 2
AO - Angola 1
AZ - Azerbaigian 1
BD - Bangladesh 1
CH - Svizzera 1
CL - Cile 1
EU - Europa 1
KZ - Kazakistan 1
MA - Marocco 1
PH - Filippine 1
PT - Portogallo 1
PY - Paraguay 1
SA - Arabia Saudita 1
TT - Trinidad e Tobago 1
Totale 6.213
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Città #
Ann Arbor 1.289
Southend 384
Singapore 259
Fairfield 224
Chandler 178
Santa Clara 177
Dong Ket 164
Ashburn 159
Wilmington 146
Jacksonville 139
Woodbridge 117
Seattle 107
Hong Kong 105
Hefei 94
Princeton 85
Cambridge 80
Houston 78
Beijing 69
Dublin 49
Boardman 46
Berlin 40
Padova 38
Turin 38
Westminster 38
Nanjing 37
Tokyo 31
Amman 26
Medford 26
Ho Chi Minh City 25
Jinan 22
Buffalo 21
Mülheim 21
Helsinki 19
Los Angeles 19
Seoul 19
Shenyang 18
Hanoi 17
San Diego 17
Saint Petersburg 16
Mahé 14
Dallas 13
Milan 13
Hebei 12
Nanchang 12
Abidjan 11
Guangzhou 11
Brussels 10
Zhengzhou 10
Changsha 9
Taizhou 9
Tianjin 9
Bologna 8
Verona 8
Ningbo 7
Bühl 6
Shanghai 6
Dearborn 5
Falkenstein 5
Frankfurt am Main 5
Haikou 5
Istanbul 5
Lanzhou 5
Lomé 5
Norwalk 5
Olalla 5
Orem 5
Sofia 5
São Paulo 5
Bengaluru 4
Des Moines 4
Jiaxing 4
Phoenix 4
Rio de Janeiro 4
Brooklyn 3
Florence 3
Fuzhou 3
Haiphong 3
Hangzhou 3
Kunming 3
Moscow 3
New York 3
Redondo Beach 3
Redwood City 3
Stockholm 3
Taiyuan 3
Amsterdam 2
Atlanta 2
Baghdad 2
Biên Hòa 2
Brasília 2
Chicago 2
Dongguan 2
Guayaquil 2
Hải Dương 2
Long An 2
Macaé 2
Maldonado 2
Ninh Bình 2
Plauen 2
Quanzhou 2
Totale 4.751
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Nome #
A Post-Compiler Approach to Scratchpad Mapping of Code 216
A Reactive and Cycle-True IP Emulator for MPSoC Exploration 211
A Layout-Aware Analysis of Networks-on-Chip and Traditional Interconnects for MPSoCs 206
A Method for Calculating Hard QoS Guarantees for Networks-on-Chip 204
An Efficient Profile-Based Algorithm for Scratchpad Memory Partitioning 203
Analyzing On-Chip Communication in a MPSoC Environment 196
Scalability Analysis of Evolving SoC Interconnect Protocols 195
Design Issues and Considerations for Low-Cost 3-D TSV IC Technology 192
Area and Power Modeling for Networks-on-Chip with Layout Awareness 191
An integrated, programming model-driven framework for NoC–QoS support in cluster-based embedded many-cores 187
Exploring architectural solutions for energy optimisations in bus-based system-on-chip 186
Characterization and Implementation of Fault-Tolerant Vertical Links for 3-D Networks-on-Chip 183
An integrated open framework for heterogeneous MPSoC design space exploration 179
Computing Accurate Performance Bounds for Best Effort Networks-on-Chip 174
Fault Tolerance Overhead in Network-on-Chip Flow Control Schemes 169
Developing Mesochronous Synchronizers to Enable 3D NoCs 169
Designing Message-Dependent Deadlock Free Networks on Chips for Application-Specific Systems on Chips 168
Comparison of a Timing-Error Tolerant Scheme with a traditional Re-transmission Mechanism for Networks on Chips 167
Designing Routing and Message-Dependent Deadlock Free Networks on Chips. 167
Bringing NoCs to 65 nm 166
Realistically Rendering SoC Traffic Patterns with Interrupt Awareness 161
NoC Design and Implementation in 65 nm Technology 159
Synthesis of low-overhead configurable source routing tables for network interfaces 159
Networks on Chips: A Synthesis Perspective 157
Timing-Error-Tolerant Network-on-Chip Design Methodology 157
A Traffic Injection Methodology with Support for System-Level Synchronization 154
Exploring programming model-driven QoS support for NoC-based platforms 149
Designing Application-Specific Networks on Chips with Floorplan Information 145
Networks-on-Chip: From Idea to Implementation 143
Network-On-Chip Design and Synthesis Outlook 143
Networks on Chips: From research to products 134
Supporting vertical links for 3D networks on chip: toward an automated design and analysis flow 134
Improving the Fault Tolerance of Nanometric PLA Designs 133
Reliability Support for On-Chip Memories Using Networks-on-Chip 132
Contrasting a NoC and a traditional interconnect fabric with layout awareness 132
Simultaneous Memory and Bus Partitioning for SoC Architectures 118
Diseño de redes en chip de propósito específico con información de rutado físico 116
xpipes Lite: A Synthesis Oriented Design Flow For Networks on Chips 89
Totale 6.244
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Categoria #
all - tutte 14.333
article - articoli 0
book - libri 0
conference - conferenze 0
curatela - curatele 0
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 0
Totale 14.333
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2020/2021417 0 0 0 0 0 28 2 35 69 40 34 209
2021/20221.869 84 12 238 212 246 199 202 195 213 49 94 125
2022/2023709 93 115 47 66 41 44 10 22 124 10 89 48
2023/2024109 11 30 6 7 7 14 7 8 2 9 3 5
2024/2025696 5 110 78 38 215 48 31 2 0 15 8 146
2025/2026767 47 157 187 87 222 67 0 0 0 0 0 0
Totale 6.244