CRIS Current Research Information System

ANGIOLINI, FEDERICO
 Distribuzione geografica
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Continente #
NA - Nord America 2.904
EU - Europa 1.270
AS - Asia 510
AF - Africa 55
OC - Oceania 2
Continente sconosciuto - Info sul continente non disponibili 1
Totale 4.742
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Nazione #
US - Stati Uniti d'America 2.904
GB - Regno Unito 431
VN - Vietnam 218
UA - Ucraina 191
DE - Germania 183
CN - Cina 181
IT - Italia 137
SE - Svezia 106
IN - India 72
FR - Francia 60
RU - Federazione Russa 50
IE - Irlanda 49
ZA - Sudafrica 28
EE - Estonia 26
JO - Giordania 26
SC - Seychelles 14
BE - Belgio 11
CI - Costa d'Avorio 8
FI - Finlandia 8
BG - Bulgaria 5
GR - Grecia 5
TG - Togo 5
TR - Turchia 5
AT - Austria 3
JP - Giappone 3
LB - Libano 3
NZ - Nuova Zelanda 2
RO - Romania 2
BD - Bangladesh 1
CH - Svizzera 1
EU - Europa 1
NL - Olanda 1
RS - Serbia 1
UZ - Uzbekistan 1
Totale 4.742
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Città #
Ann Arbor 1.289
Southend 384
Fairfield 224
Chandler 178
Dong Ket 164
Wilmington 146
Ashburn 141
Jacksonville 139
Woodbridge 117
Seattle 106
Princeton 85
Cambridge 80
Houston 78
Dublin 49
Berlin 38
Padova 38
Turin 38
Westminster 38
Nanjing 35
Amman 26
Medford 26
Jinan 22
Mülheim 21
San Diego 17
Shenyang 17
Saint Petersburg 16
Mahé 14
Milan 13
Hebei 12
Nanchang 12
Brussels 10
Zhengzhou 10
Beijing 9
Taizhou 9
Tianjin 9
Abidjan 8
Boardman 8
Bologna 8
Verona 8
Changsha 7
Helsinki 7
Bühl 6
Dearborn 5
Haikou 5
Istanbul 5
Lanzhou 5
Lomé 5
Norwalk 5
Olalla 5
Sofia 5
Des Moines 4
Guangzhou 4
Jiaxing 4
Ningbo 4
Florence 3
Hangzhou 3
Redwood City 3
Tokyo 3
Kunming 2
Los Angeles 2
Plauen 2
Taiyuan 2
Washington 2
Antwerp 1
Belgrade 1
Bern 1
Cedar Knolls 1
Chicago 1
Christchurch 1
Dhaka 1
Falls Church 1
Frankfurt Am Main 1
Fuzhou 1
Genzano Di Roma 1
Grafing 1
Groningen 1
Hefei 1
Inglewood 1
Kiev 1
Kilburn 1
Lappeenranta 1
Las Vegas 1
London 1
New Orleans 1
Orange 1
Pettorazza Grimani 1
Phoenix 1
Provo 1
Puxian 1
Redmond 1
Rome 1
Stockholm 1
Tappahannock 1
Xian 1
Yicheng 1
Totale 3.772
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Nome #
A Reactive and Cycle-True IP Emulator for MPSoC Exploration 174
A Layout-Aware Analysis of Networks-on-Chip and Traditional Interconnects for MPSoCs 169
A Post-Compiler Approach to Scratchpad Mapping of Code 166
A Method for Calculating Hard QoS Guarantees for Networks-on-Chip 166
An Efficient Profile-Based Algorithm for Scratchpad Memory Partitioning 158
Area and Power Modeling for Networks-on-Chip with Layout Awareness 157
Analyzing On-Chip Communication in a MPSoC Environment 153
An integrated, programming model-driven framework for NoC–QoS support in cluster-based embedded many-cores 151
Characterization and Implementation of Fault-Tolerant Vertical Links for 3-D Networks-on-Chip 148
An integrated open framework for heterogeneous MPSoC design space exploration 143
Design Issues and Considerations for Low-Cost 3-D TSV IC Technology 143
Exploring architectural solutions for energy optimisations in bus-based system-on-chip 141
Comparison of a Timing-Error Tolerant Scheme with a traditional Re-transmission Mechanism for Networks on Chips 135
Scalability Analysis of Evolving SoC Interconnect Protocols 134
Developing Mesochronous Synchronizers to Enable 3D NoCs 134
Computing Accurate Performance Bounds for Best Effort Networks-on-Chip 134
Designing Message-Dependent Deadlock Free Networks on Chips for Application-Specific Systems on Chips 128
Designing Routing and Message-Dependent Deadlock Free Networks on Chips. 126
A Traffic Injection Methodology with Support for System-Level Synchronization 126
Timing-Error-Tolerant Network-on-Chip Design Methodology 125
Synthesis of low-overhead configurable source routing tables for network interfaces 125
Fault Tolerance Overhead in Network-on-Chip Flow Control Schemes 123
Bringing NoCs to 65 nm 123
Designing Application-Specific Networks on Chips with Floorplan Information 113
NoC Design and Implementation in 65 nm Technology 112
Network-On-Chip Design and Synthesis Outlook 112
Realistically Rendering SoC Traffic Patterns with Interrupt Awareness 110
Contrasting a NoC and a traditional interconnect fabric with layout awareness 106
Networks on Chips: A Synthesis Perspective 103
Reliability Support for On-Chip Memories Using Networks-on-Chip 103
Networks on Chips: From research to products 102
Supporting vertical links for 3D networks on chip: toward an automated design and analysis flow 101
Exploring programming model-driven QoS support for NoC-based platforms 100
Networks-on-Chip: From Idea to Implementation 97
Improving the Fault Tolerance of Nanometric PLA Designs 97
Simultaneous Memory and Bus Partitioning for SoC Architectures 93
Diseño de redes en chip de propósito específico con información de rutado físico 89
xpipes Lite: A Synthesis Oriented Design Flow For Networks on Chips 53
Totale 4.773
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Categoria #
all - tutte 8.935
article - articoli 0
book - libri 0
conference - conferenze 0
curatela - curatele 0
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 0
Totale 8.935
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2018/201959 0 0 0 0 0 0 0 0 0 0 22 37
2019/20201.066 173 25 24 77 97 111 123 149 118 71 36 62
2020/2021644 124 49 15 35 4 28 2 35 69 40 34 209
2021/20221.869 84 12 238 212 246 199 202 195 213 49 94 125
2022/2023709 93 115 47 66 41 44 10 22 124 10 89 48
2023/2024101 11 30 6 7 7 14 7 8 2 9 0 0
Totale 4.773