ANGIOLINI, FEDERICO
ANGIOLINI, FEDERICO
An integrated, programming model-driven framework for NoC–QoS support in cluster-based embedded many-cores
2013 J. Joven;A. Marongiu;F. Angiolini;L. Benini;G. De Micheli
Computing Accurate Performance Bounds for Best Effort Networks-on-Chip
2013 Rahmati D., Murali S. ; Benini L. ; Angiolini F. ; De Micheli G. ; Sarbazi-Azad H.
Characterization and Implementation of Fault-Tolerant Vertical Links for 3-D Networks-on-Chip
2011 Loi I.; Angiolini F.; Fujita S.; Mitra S.; Benini L.
Design Issues and Considerations for Low-Cost 3-D TSV IC Technology
2011 Van der Plas G.; Limaye P.; Loi I.; Mercha A.; Oprins H.; Torregiani C.; Thijs S.; Linten D.; Stucchi M.; Katti G.; Velenis D.; Cherman V.; Vandevelde B.; Simons V.; De Wolf I.; Labie R.; Perry D.; Bronckers S.; Minas N.; Cupac M.; Ruythooren W.; Van Olmen J.; Phommahaxay A.; de Potter de ten Broeck M.; Opdebeeck A.; Rakowski M.; De Wachter B.; Dehan M.; Nelis M.; Agarwal R.; Pullini A.; Angiolini F.; Benini L.; Dehaene W.; Travaly Y.; Beyne E.; Marchal P.
Exploring programming model-driven QoS support for NoC-based platforms
2010 J. Joven; A. Marongiu; F. Angiolini; L. Benini; G. De Micheli
Networks on Chips: From research to products
2010 De Micheli G. ; Seiculescu C. ; Murali S. ; Benini L. ; Angiolini F. ; Pullini A.
A Method for Calculating Hard QoS Guarantees for Networks-on-Chip
2009 D. Rahmati; S. Murali; L. Benini; F. Angiolini; G. De Micheli; H. Sarbazi-Azad
Synthesis of low-overhead configurable source routing tables for network interfaces
2009 Loi I.; Angiolini F.; Benini L.
A Reactive and Cycle-True IP Emulator for MPSoC Exploration
2008 S. Mahadevan; F. Angiolini; J. Sparsø; L. Benini; J. Madsen
Designing Routing and Message-Dependent Deadlock Free Networks on Chips.
2008 S. Murali; P. Meloni; F. Angiolini; D. Atienza; S. Carta; L. Benini; G. De Micheli; L. Raffo.
Developing Mesochronous Synchronizers to Enable 3D NoCs
2008 I. Loi; F. Angiolini; L. Benini
Exploring architectural solutions for energy optimisations in bus-based system-on-chip
2008 S. Srinivasan; L. Li; M. Ruggiero; F. Angiolini; N. Vijaykrishnan; L. Benini
Network-On-Chip Design and Synthesis Outlook
2008 D. Atienza; F. Angiolini; S. Murali; A. Pullini; L. Benini; G. De Micheli
A Layout-Aware Analysis of Networks-on-Chip and Traditional Interconnects for MPSoCs
2007 F. Angiolini; P. Meloni; S. Carta; L. Raffo; L. Benini
A Traffic Injection Methodology with Support for System-Level Synchronization
2007 S. Mahadevan; F. Angiolini; J. Sparsø; L. Benini; J. Madsen
Area and Power Modeling for Networks-on-Chip with Layout Awareness
2007 P. Meloni; I. Loi; F. Angiolini; S. Carta; M. Barbaro; L. Raffo; L. Benini
Bringing NoCs to 65 nm
2007 A. Pullini; F. Angiolini; S. Murali; D. Atienza; G. De Micheli; L. Benini
Improving the Fault Tolerance of Nanometric PLA Designs
2007 F. Angiolini; H. Ben Jamaa; D. Atienza; L. Benini; G. De Micheli
Networks-on-Chip: From Idea to Implementation
2007 F. Angiolini; L. Benini
NoC Design and Implementation in 65 nm Technology
2007 A. Pullini; F. Angiolini; P. Meloni; D. Atienza; S. Murali; L. Raffo; G. De Micheli; L. Benini;
| Titolo | Autore(i) | Anno | Periodico | Editore | Tipo | File |
|---|---|---|---|---|---|---|
| An integrated, programming model-driven framework for NoC–QoS support in cluster-based embedded many-cores | J. Joven;A. Marongiu;F. Angiolini;L. Benini;G. De Micheli | 2013-01-01 | PARALLEL COMPUTING | - | 1.01 Articolo in rivista | - |
| Computing Accurate Performance Bounds for Best Effort Networks-on-Chip | Rahmati D., Murali S. ; Benini L. ; Angiolini F. ; De Micheli G. ; Sarbazi-Azad H. | 2013-01-01 | IEEE TRANSACTIONS ON COMPUTERS | - | 1.01 Articolo in rivista | - |
| Characterization and Implementation of Fault-Tolerant Vertical Links for 3-D Networks-on-Chip | Loi I.; Angiolini F.; Fujita S.; Mitra S.; Benini L. | 2011-01-01 | IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS | - | 1.01 Articolo in rivista | - |
| Design Issues and Considerations for Low-Cost 3-D TSV IC Technology | Van der Plas G.; Limaye P.; Loi I.; Mercha A.; Oprins H.; Torregiani C.; Thijs S.; Linten D.; Stu...cchi M.; Katti G.; Velenis D.; Cherman V.; Vandevelde B.; Simons V.; De Wolf I.; Labie R.; Perry D.; Bronckers S.; Minas N.; Cupac M.; Ruythooren W.; Van Olmen J.; Phommahaxay A.; de Potter de ten Broeck M.; Opdebeeck A.; Rakowski M.; De Wachter B.; Dehan M.; Nelis M.; Agarwal R.; Pullini A.; Angiolini F.; Benini L.; Dehaene W.; Travaly Y.; Beyne E.; Marchal P. | 2011-01-01 | IEEE JOURNAL OF SOLID-STATE CIRCUITS | - | 1.01 Articolo in rivista | - |
| Exploring programming model-driven QoS support for NoC-based platforms | J. Joven; A. Marongiu; F. Angiolini; L. Benini; G. De Micheli | 2010-01-01 | - | ACM | 4.01 Contributo in Atti di convegno | - |
| Networks on Chips: From research to products | De Micheli G. ; Seiculescu C. ; Murali S. ; Benini L. ; Angiolini F. ; Pullini A. | 2010-01-01 | - | ACM/IEEE | 4.01 Contributo in Atti di convegno | - |
| A Method for Calculating Hard QoS Guarantees for Networks-on-Chip | D. Rahmati; S. Murali; L. Benini; F. Angiolini; G. De Micheli; H. Sarbazi-Azad | 2009-01-01 | - | ACM | 4.01 Contributo in Atti di convegno | - |
| Synthesis of low-overhead configurable source routing tables for network interfaces | Loi I.; Angiolini F.; Benini L. | 2009-01-01 | - | IEEE Press | 4.01 Contributo in Atti di convegno | - |
| A Reactive and Cycle-True IP Emulator for MPSoC Exploration | S. Mahadevan; F. Angiolini; J. Sparsø; L. Benini; J. Madsen | 2008-01-01 | IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS | - | 1.01 Articolo in rivista | - |
| Designing Routing and Message-Dependent Deadlock Free Networks on Chips. | S. Murali; P. Meloni; F. Angiolini; D. Atienza; S. Carta; L. Benini; G. De Micheli; L. Raffo. | 2008-01-01 | - | Springer | 4.01 Contributo in Atti di convegno | - |
| Developing Mesochronous Synchronizers to Enable 3D NoCs | I. Loi; F. Angiolini; L. Benini | 2008-01-01 | - | s.n | 4.01 Contributo in Atti di convegno | - |
| Exploring architectural solutions for energy optimisations in bus-based system-on-chip | S. Srinivasan; L. Li; M. Ruggiero; F. Angiolini; N. Vijaykrishnan; L. Benini | 2008-01-01 | IET COMPUTERS & DIGITAL TECHNIQUES | - | 1.01 Articolo in rivista | - |
| Network-On-Chip Design and Synthesis Outlook | D. Atienza; F. Angiolini; S. Murali; A. Pullini; L. Benini; G. De Micheli | 2008-01-01 | INTEGRATION | - | 1.01 Articolo in rivista | - |
| A Layout-Aware Analysis of Networks-on-Chip and Traditional Interconnects for MPSoCs | F. Angiolini; P. Meloni; S. Carta; L. Raffo; L. Benini | 2007-01-01 | IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS | - | 1.01 Articolo in rivista | - |
| A Traffic Injection Methodology with Support for System-Level Synchronization | S. Mahadevan; F. Angiolini; J. Sparsø; L. Benini; J. Madsen | 2007-01-01 | - | Springer Boston | 2.01 Capitolo / saggio in libro | - |
| Area and Power Modeling for Networks-on-Chip with Layout Awareness | P. Meloni; I. Loi; F. Angiolini; S. Carta; M. Barbaro; L. Raffo; L. Benini | 2007-01-01 | VLSI DESIGN | - | 1.01 Articolo in rivista | - |
| Bringing NoCs to 65 nm | A. Pullini; F. Angiolini; S. Murali; D. Atienza; G. De Micheli; L. Benini | 2007-01-01 | IEEE MICRO | - | 1.01 Articolo in rivista | - |
| Improving the Fault Tolerance of Nanometric PLA Designs | F. Angiolini; H. Ben Jamaa; D. Atienza; L. Benini; G. De Micheli | 2007-01-01 | - | s.n | 4.01 Contributo in Atti di convegno | - |
| Networks-on-Chip: From Idea to Implementation | F. Angiolini; L. Benini | 2007-01-01 | - | s.n | 4.02 Riassunto (Abstract) | - |
| NoC Design and Implementation in 65 nm Technology | A. Pullini; F. Angiolini; P. Meloni; D. Atienza; S. Murali; L. Raffo; G. De Micheli; L. Benini; | 2007-01-01 | - | IEEE Circuits and Systems Society | 4.01 Contributo in Atti di convegno | - |