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EnglishResearch on Networks on Chips (NoCs) has spanned over a decade and its results are now visible in some products. Thus the seminal idea of using networking technology to address the chip-level interconnect problem has been shown to be correct. Moreover, as technology scales down in geometry and chips scale up in complexity, NoCs become the essential element to achieve the desired levels of performance and quality of service while curbing power consumption levels. Design and timing closure can only be achieved by a sophisticated set of tools that address NoC synthesis, optimization and validation.
| Titolo: | Networks on Chips: From research to products | |
| Autore/i: | De Micheli G.; Seiculescu C.; Murali S.; BENINI, LUCA; ANGIOLINI, FEDERICO; Pullini A. | |
| Autore/i Unibo: | ||
| Anno: | 2010 | |
| Titolo del libro: | Design Automation Conference (DAC), 2010 47th ACM/IEEE | |
| Pagina iniziale: | 300 | |
| Pagina finale: | 305 | |
| Abstract: | Research on Networks on Chips (NoCs) has spanned over a decade and its results are now visible in some products. Thus the seminal idea of using networking technology to address the chip-level interconnect problem has been shown to be correct. Moreover, as technology scales down in geometry and chips scale up in complexity, NoCs become the essential element to achieve the desired levels of performance and quality of service while curbing power consumption levels. Design and timing closure can only be achieved by a sophisticated set of tools that address NoC synthesis, optimization and validation. | |
| Data prodotto definitivo in UGOV: | 23-dic-2010 | |
| Appare nelle tipologie: | 4.01 Contributo in Atti di convegno |
File in questo prodotto:
http://hdl.handle.net/11585/95314
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