A numerical investigation of the hot-carrier behavior of a lateral DMOS transistor with shallow trench isolation (STI) is carried out. The measured drain-current degradation induced by hot-carrier stress (HCS) is nicely reproduced by TCAD results revealing that interface traps are mainly formed at the STI corner close to the channel. The effect of typical device design variations on hot-carrier degradation is analyzed.

Analysis of HCS in STI-based LDMOS transistors

REGGIANI, SUSANNA;POLI, STEFANO;GNANI, ELENA;GNUDI, ANTONIO;BACCARANI, GIORGIO;
2010

Abstract

A numerical investigation of the hot-carrier behavior of a lateral DMOS transistor with shallow trench isolation (STI) is carried out. The measured drain-current degradation induced by hot-carrier stress (HCS) is nicely reproduced by TCAD results revealing that interface traps are mainly formed at the STI corner close to the channel. The effect of typical device design variations on hot-carrier degradation is analyzed.
Proceedings of the International Reliability Physics Symposium (IRPS 2010)
881
884
S. Reggiani; S. Poli; E. Gnani; A. Gnudi; G. Baccarani; M. Denison; S. Pendharkar; R. Wise; S. Seetharaman
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11585/93237
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