Graphene-Based High-Performance Nanoelectronic Devices

In this paper we perform a simulation study on the limits of graphene nanoribbon (GNR) FETs. Both conventional and tunnelling FET architectures are taken into account. Simulations of conventional narrow GNR FETs confirm the high potential of these devices, but highlight at the same time OFF-state leakage problems due to various tunnelling mechanisms, which become more severe as the width is made larger and require a careful device optimization. Such OFF-state problems are partially solved by the tunnelling FETs, which allow subthreshold slopes better than 60 mV/dec, at the price of a reduced ON current. The importance of a very good control on edge roughness is also highlighted through direct simulation of devices with non-ideal edges.