This paper investigates the circuit-level performance of an inverter made by n- and p-type tunnel field-effect transistors (TFETs), integrated on the same InAs/Al0.05Ga0.95Sb technology platform, in the presence of interface traps and localized strain. From 3-D full-quantum simulations, interface traps are found to induce a significant degradation of the voltage gain, noise margin and transient performance. The effect of localized strain at the source/channel heterojunction caused by lattice mismatch, although beneficial, is unable to recover the circuit-level performance of the ideal case.
TFET-based inverter performance in the presence of traps and localized strain / Gnani, E.; Gnudi, A.; Reggiani, S.; Baccarani, G.; Visciarelli, M.. - ELETTRONICO. - 2018-:(2018), pp. 1-4. (Intervento presentato al convegno 2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2018 tenutosi a esp nel 2018) [10.1109/ULIS.2018.8354726].
TFET-based inverter performance in the presence of traps and localized strain
Gnani, E.
;Gnudi, A.;Reggiani, S.;Baccarani, G.;Visciarelli, M.
2018
Abstract
This paper investigates the circuit-level performance of an inverter made by n- and p-type tunnel field-effect transistors (TFETs), integrated on the same InAs/Al0.05Ga0.95Sb technology platform, in the presence of interface traps and localized strain. From 3-D full-quantum simulations, interface traps are found to induce a significant degradation of the voltage gain, noise margin and transient performance. The effect of localized strain at the source/channel heterojunction caused by lattice mismatch, although beneficial, is unable to recover the circuit-level performance of the ideal case.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
