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EnglishA simulation study on the impact of interface traps and strain on the I - V characteristics of co-optimized p- and n-type tunnel FETs (TFETs) realized on the same InAs/Al0.05Ga0.95Sb technology platform is carried out, using a full-quantum ballistic simulator. In order to capture the effect of interface/border traps on the device electrostatics consistently with carrier degeneracy and ballistic transport, the classical Shockley-Read-Hall theory has been properly generalized. The effect of an experimental Dit distribution of a high-k gate stacks on InAs has been investigated. Unfortunately, traps induce a significant reduction of the ON-state current. However, it turns out that localized strain at the source/channel heterojunction caused by lattice mismatch is able to induce for the n-type TFET, a performance enhancement with respect to the ideal device even in the presence of traps. On the contrary, for the p-type one, a current degradation â 18 % is observed.
| Titolo: | Impact of Traps and Strain on Optimized n- and p-Type TFETs Integrated on the Same InAs/AlGaSb Technology Platform | |
| Autore/i: | Visciarelli, Michele; Gnani, Elena; Gnudi, Antonio; Reggiani, Susanna; Baccarani, Giorgio | |
| Autore/i Unibo: | ||
| Anno: | 2017 | |
| Rivista: | ||
| Digital Object Identifier (DOI): | http://dx.doi.org/10.1109/TED.2017.2711779 | |
| Abstract: | A simulation study on the impact of interface traps and strain on the I - V characteristics of co-optimized p- and n-type tunnel FETs (TFETs) realized on the same InAs/Al0.05Ga0.95Sb technology platform is carried out, using a full-quantum ballistic simulator. In order to capture the effect of interface/border traps on the device electrostatics consistently with carrier degeneracy and ballistic transport, the classical Shockley-Read-Hall theory has been properly generalized. The effect of an experimental Dit distribution of a high-k gate stacks on InAs has been investigated. Unfortunately, traps induce a significant reduction of the ON-state current. However, it turns out that localized strain at the source/channel heterojunction caused by lattice mismatch is able to induce for the n-type TFET, a performance enhancement with respect to the ideal device even in the presence of traps. On the contrary, for the p-type one, a current degradation â 18 % is observed. | |
| Data stato definitivo: | 2017-11-16T16:10:29Z | |
| Appare nelle tipologie: | 1.01 Articolo in rivista |
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http://hdl.handle.net/11585/610866
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