The ultimate scaling limits of p-i-n carbon-nanotube field-effect transistors (CNT-FETs) are investigated through numerical simulations based on a quantum–mechanical transport within the nonequilibrium Green’s function formalism, based on an energy-dependent effective mass, including inelastic phonon scattering. Starting from the projected specifications of the International Technology Roadmap for Semiconductors for the low operating-power double-gate MOSFETs, the effect of variations of oxide thickness, power supply, and gate length has been systematically studied. The main conclusion is that there is no speed advantage in scaling the gate length of the p-i-n CNT-FETs below 16 nm due to the rapid increase of the tunneling current in the subthreshold region. A near optimum is found by keeping the gate length fixed at 16 nm and by scaling the oxide thickness and the power supply.
S. Poli, S. Reggiani, A. Gnudi, E. Gnani, G. Baccarani (2008). Computational study of the ultimate scaling limits of CNT tunneling devices. IEEE TRANSACTIONS ON ELECTRON DEVICES, 55, 313-321 [10.1109/TED.2007.910563].
Computational study of the ultimate scaling limits of CNT tunneling devices
POLI, STEFANO;REGGIANI, SUSANNA;GNUDI, ANTONIO;GNANI, ELENA;BACCARANI, GIORGIO
2008
Abstract
The ultimate scaling limits of p-i-n carbon-nanotube field-effect transistors (CNT-FETs) are investigated through numerical simulations based on a quantum–mechanical transport within the nonequilibrium Green’s function formalism, based on an energy-dependent effective mass, including inelastic phonon scattering. Starting from the projected specifications of the International Technology Roadmap for Semiconductors for the low operating-power double-gate MOSFETs, the effect of variations of oxide thickness, power supply, and gate length has been systematically studied. The main conclusion is that there is no speed advantage in scaling the gate length of the p-i-n CNT-FETs below 16 nm due to the rapid increase of the tunneling current in the subthreshold region. A near optimum is found by keeping the gate length fixed at 16 nm and by scaling the oxide thickness and the power supply.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
