The sensitivity of HV RESURF LDMOS transistors to parasitic charging in molding compound is investigated in this work by incorporating the passivation and encapsulation layers in the TCAD setup and implementing the conductivity losses in the mold. The role played by field plates and multiple metal/poly-silicon floating rings on the overall RESURF are revisited by focusing on the breakdown voltage degradation under high-voltage, high-temperature stresses. The layout re-optimization of a Single- and a Triple-RESURF LDMOS device using only MET1and poly-Si levels is presented to reach a stable breakdown voltage after HTRB stress.
Arienti, G., Imperiale, I., Reggiani, S., Gnani, E., Gnudi, A., Baccarani, G., et al. (2015). Optimization of HV LDMOS devices accounting for packaging interaction. Institute of Electrical and Electronics Engineers Inc. [10.1109/ISPSD.2015.7123450].
Optimization of HV LDMOS devices accounting for packaging interaction
IMPERIALE, ILARIA;REGGIANI, SUSANNA;GNANI, ELENA;GNUDI, ANTONIO;BACCARANI, GIORGIO;
2015
Abstract
The sensitivity of HV RESURF LDMOS transistors to parasitic charging in molding compound is investigated in this work by incorporating the passivation and encapsulation layers in the TCAD setup and implementing the conductivity losses in the mold. The role played by field plates and multiple metal/poly-silicon floating rings on the overall RESURF are revisited by focusing on the breakdown voltage degradation under high-voltage, high-temperature stresses. The layout re-optimization of a Single- and a Triple-RESURF LDMOS device using only MET1and poly-Si levels is presented to reach a stable breakdown voltage after HTRB stress.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
