A novel approach to optimize tunnel field effect transistors (TFETs) by technology computer aided design simulations is reported. The most interesting outcome of our design effort is a dual metal gate (DMG) TFET, which features an inverse subthreshold slope (SS) significantly < 60 mV/decade over more than five orders of magnitude of drain current, with a minimum value of 6 mV/decade sustained across one drain current decade or more. The DMGTFET simultaneously fulfills both the low-stand-by-power off-state current and the high-performance on-state current at a supply voltage of 0.5 V. Therefore, 25% reduction of static power consumption is expected compared with the 2020 International Technology Roadmap for Semiconductors requirements for multigate transistors.