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EnglishA novel approach to optimize tunnel field effect transistors (TFETs) by technology computer aided design simulations is reported. The most interesting outcome of our design effort is a dual metal gate (DMG) TFET, which features an inverse subthreshold slope (SS) significantly < 60 mV/decade over more than five orders of magnitude of drain current, with a minimum value of 6 mV/decade sustained across one drain current decade or more. The DMGTFET simultaneously fulfills both the low-stand-by-power off-state current and the high-performance on-state current at a supply voltage of 0.5 V. Therefore, 25% reduction of static power consumption is expected compared with the 2020 International Technology Roadmap for Semiconductors requirements for multigate transistors.
| Titolo: | Dual-Metal-Gate InAs Tunnel FET With Enhanced Turn-On Steepness and High On-Current |
| Autore/i: | BETTI BENEVENTI, GIOVANNI; GNANI, ELENA; GNUDI, ANTONIO; REGGIANI, SUSANNA; BACCARANI, GIORGIO |
| Autore/i Unibo: | |
| Anno: | 2014 |
| Rivista: | |
| Digital Object Identifier (DOI): | http://dx.doi.org/10.1109/TED.2014.2298212 |
| Abstract: | A novel approach to optimize tunnel field effect transistors (TFETs) by technology computer aided design simulations is reported. The most interesting outcome of our design effort is a dual metal gate (DMG) TFET, which features an inverse subthreshold slope (SS) significantly < 60 mV/decade over more than five orders of magnitude of drain current, with a minimum value of 6 mV/decade sustained across one drain current decade or more. The DMGTFET simultaneously fulfills both the low-stand-by-power off-state current and the high-performance on-state current at a supply voltage of 0.5 V. Therefore, 25% reduction of static power consumption is expected compared with the 2020 International Technology Roadmap for Semiconductors requirements for multigate transistors. |
| Data stato definitivo: | 2015-11-13T17:31:53Z |
| Appare nelle tipologie: | 1.01 Articolo in rivista |
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