The linear drain current degradation due to hot-carrier stress (HCS) of an n-type LDMOS with shallow-trench isolation (STI) has been investigated through experiments and TCAD predictions under AC pulsed stress conditions. The systematic increase of degradation with frequency and the dependence on rise/fall times and duty cycle has been explained by using a new TCAD approach based on physical models. The degradation increase can be correlated to the peak of the HCS reaction rate at the rising edge. The analysis carried out on two different devices confirms the TCAD predictions.
Linear drain current degradation of STI-based LDMOS transistors under AC stress conditions / S. Reggiani; F. Monti; G. Barone; E. Gnani; A. Gnudi; G. Baccarani; S. Poli; M.-Y. Chuang; W. Tian; R. Wise. - STAMPA. - (2014), pp. 193-196. (Intervento presentato al convegno 2014 IEEE 26th International Symposium on Power Semiconductor Devices & IC's (ISPSD) tenutosi a Waikoloa, Hawaii (USA) nel June 15-19, 2014) [10.1109/ISPSD.2014.6856009].
Linear drain current degradation of STI-based LDMOS transistors under AC stress conditions
REGGIANI, SUSANNA;MONTI, FEDERICO;GNANI, ELENA;GNUDI, ANTONIO;BACCARANI, GIORGIO;
2014
Abstract
The linear drain current degradation due to hot-carrier stress (HCS) of an n-type LDMOS with shallow-trench isolation (STI) has been investigated through experiments and TCAD predictions under AC pulsed stress conditions. The systematic increase of degradation with frequency and the dependence on rise/fall times and duty cycle has been explained by using a new TCAD approach based on physical models. The degradation increase can be correlated to the peak of the HCS reaction rate at the rising edge. The analysis carried out on two different devices confirms the TCAD predictions.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
