Design of a suitable technology platform is carried out in this paper for co-integration of simultaneously optimized n-and p-type tunnel field-effect transistors (TFETs). InAs/AlxGa1-xSb heterostructures are considered, and a 3-D full-quantum simulation approach is adopted to investigate the combined effect of Al mole fraction x and transverse quantization on band lineups at the heterojunction. Design optimization leads to a TFET pair with similar dimensions and feasible aspect ratios realized on the same InAs/Al 0.05Ga0.95Sb platform. These devices exhibit average subthreshold slopes below 60 mV/dec and relatively high ON-currents of 270 (n-TFET) and 120 μA/μm (p-TFET) at a low-supply voltage VDD =0.4 V. Combined ON-and OFF-state performance of the proposed technology platform is expected to be compatible with low operating power applications, while potential candidates for low standby power scenarios are obtained by reducing TFET cross sections from 10 to 7 nm.
Emanuele, B., Elena, G., Roberto, G., Antonio, G., Susanna, R., Giorgio, B. (2014). Optimization of n-and p-type TFETs integrated on the same InAs/Al xGa1-xSb technology platform. IEEE TRANSACTIONS ON ELECTRON DEVICES, 61, 178-185 [10.1109/TED.2013.2289739].
Optimization of n-and p-type TFETs integrated on the same InAs/Al xGa1-xSb technology platform
BARAVELLI, EMANUELE;GNANI, ELENA;GRASSI, ROBERTO;GNUDI, ANTONIO;REGGIANI, SUSANNA;BACCARANI, GIORGIO
2014
Abstract
Design of a suitable technology platform is carried out in this paper for co-integration of simultaneously optimized n-and p-type tunnel field-effect transistors (TFETs). InAs/AlxGa1-xSb heterostructures are considered, and a 3-D full-quantum simulation approach is adopted to investigate the combined effect of Al mole fraction x and transverse quantization on band lineups at the heterojunction. Design optimization leads to a TFET pair with similar dimensions and feasible aspect ratios realized on the same InAs/Al 0.05Ga0.95Sb platform. These devices exhibit average subthreshold slopes below 60 mV/dec and relatively high ON-currents of 270 (n-TFET) and 120 μA/μm (p-TFET) at a low-supply voltage VDD =0.4 V. Combined ON-and OFF-state performance of the proposed technology platform is expected to be compatible with low operating power applications, while potential candidates for low standby power scenarios are obtained by reducing TFET cross sections from 10 to 7 nm.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
