Design of complementary n- and p-type heterojunction tunnel field-effect transistors (TFETs) realized with the same InAs/Al0.05Ga0.95Sb material pair is carried out in this work using 3D, full-quantum simulations. Several design parameters are optimized, leading to a TFET pair with similar dimensions and feasible aspect ratios, which exhibit average subthreshold slopes around 30 mV/dec and relatively high on-currents of 280 (n-TFET) and 165 μA/ μm (p-TFET) at 0.4 V supply voltage. This is combined with low operating power (LOP) compatible off-currents, which makes the proposed technology platform well suited for LOP applications and even usable in HP scenarios. Devices with reduced cross section (7 nm instead of 10 nm) are also proposed as good candidates for low standby power (LSTP) scenarios.
Complementary n- and p-type TFETs on the same InAs/Al(0.05)Ga(0.95)Sb platform / E. Baravelli;E. Gnani;R. Grassi;A. Gnudi;S. Reggiani;G. Baccarani. - ELETTRONICO. - (2013), pp. 69-72. (Intervento presentato al convegno European Solid-State Device Research Conference (ESSDERC) tenutosi a Bucharest nel 16-20 Sept. 2013) [10.1109/ESSDERC.2013.6818821].
Complementary n- and p-type TFETs on the same InAs/Al(0.05)Ga(0.95)Sb platform
BARAVELLI, EMANUELE;GNANI, ELENA;GRASSI, ROBERTO;GNUDI, ANTONIO;REGGIANI, SUSANNA;BACCARANI, GIORGIO
2013
Abstract
Design of complementary n- and p-type heterojunction tunnel field-effect transistors (TFETs) realized with the same InAs/Al0.05Ga0.95Sb material pair is carried out in this work using 3D, full-quantum simulations. Several design parameters are optimized, leading to a TFET pair with similar dimensions and feasible aspect ratios, which exhibit average subthreshold slopes around 30 mV/dec and relatively high on-currents of 280 (n-TFET) and 165 μA/ μm (p-TFET) at 0.4 V supply voltage. This is combined with low operating power (LOP) compatible off-currents, which makes the proposed technology platform well suited for LOP applications and even usable in HP scenarios. Devices with reduced cross section (7 nm instead of 10 nm) are also proposed as good candidates for low standby power (LSTP) scenarios.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
