Modeling and characterization of hot-carrier stress degradation in power MOSFETs

Power device reliability is one of the key challenges of next generation Smart-Power technologies. As a consequence, device performance needs to be optimized accounting for hot-carrier stress degradation issues. To this purpose, numerical simulation tools are commonly used, but the TCAD modeling of performance drifts due to electrical stress is still an open issue. Physics-based analytical models and TCAD based approaches have been proposed and devised for the investigation of the parameter degradation in the linear transport regime and its localization in STI-based LDMOS devices. A thorough investigation of the degradation under high-gate stress biases, corresponding to impact-ionization regimes, is carried out to gain an insight on the overall bias and temperature dependence of the parameter drifts.