A scalable Dual n/p-LDMOS device with interesting Rsp versus Vbd performance for voltage applications in the range of 20–120 V is identified through proper optimization. Three designs have been proposed, based on different process implementations. The physical behavior of the device is reviewed and analyzed. The current expansion induced by the bipolar conductance in the drift region at high gate and drain biases is fully explained. The thermal behavior in a worst case condition is investigated, and the reduction in performance in terms of current and safe-operating area are reported. The switching performance is addressed, showing very good transient times in any analyzed load condition.
Optimization and Analysis of the Dual n/p-LDMOS Device / S. Poli; S. Reggiani; R.K. Sharma; M. Denison; E. Gnani; A. Gnudi; G. Baccarani. - In: IEEE TRANSACTIONS ON ELECTRON DEVICES. - ISSN 0018-9383. - STAMPA. - 59:(2012), pp. 745-753. [10.1109/TED.2011.2178189]
Optimization and Analysis of the Dual n/p-LDMOS Device
POLI, STEFANO;REGGIANI, SUSANNA;GNANI, ELENA;GNUDI, ANTONIO;BACCARANI, GIORGIO
2012
Abstract
A scalable Dual n/p-LDMOS device with interesting Rsp versus Vbd performance for voltage applications in the range of 20–120 V is identified through proper optimization. Three designs have been proposed, based on different process implementations. The physical behavior of the device is reviewed and analyzed. The current expansion induced by the bipolar conductance in the drift region at high gate and drain biases is fully explained. The thermal behavior in a worst case condition is investigated, and the reduction in performance in terms of current and safe-operating area are reported. The switching performance is addressed, showing very good transient times in any analyzed load condition.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
