The physical behavior of the dual N/P-LDMOS device concept is reviewed and analyzed. Through a proper optimization, a scalable device with good RSP vs. VBD performance in a range of 20–150 V is identified. Further, the current expansion at high gate and drain biases is fully explained by means of TCAD simulations and nicely exploited for the design of an LDO linear voltage regulator with excellent performance in terms of both drop-out voltage and maximum load current.

S. Poli, S. Reggiani, R. K. Sharma, G. Baccarani, E. Gnani, A. Gnudi, et al. (2011). TCAD optimization of a dual N/P-LDMOS transistor. Piscataway : IEEE Publishing Services [10.1109/ESSDERC.2011.6044188].

TCAD optimization of a dual N/P-LDMOS transistor

POLI, STEFANO;REGGIANI, SUSANNA;BACCARANI, GIORGIO;GNANI, ELENA;GNUDI, ANTONIO;
2011

Abstract

The physical behavior of the dual N/P-LDMOS device concept is reviewed and analyzed. Through a proper optimization, a scalable device with good RSP vs. VBD performance in a range of 20–150 V is identified. Further, the current expansion at high gate and drain biases is fully explained by means of TCAD simulations and nicely exploited for the design of an LDO linear voltage regulator with excellent performance in terms of both drop-out voltage and maximum load current.
2011
Proceedings of the 41st European Solid-State Device Research Conference
247
250
S. Poli, S. Reggiani, R. K. Sharma, G. Baccarani, E. Gnani, A. Gnudi, et al. (2011). TCAD optimization of a dual N/P-LDMOS transistor. Piscataway : IEEE Publishing Services [10.1109/ESSDERC.2011.6044188].
S. Poli; S. Reggiani; R. K. Sharma; G. Baccarani; E. Gnani; A. Gnudi; M. Denison
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11585/106875
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