statistiche ricercatore

Nome	#
A resilient architecture for low latency communication in shared-L1 processor clusters	176
A fully-synthesizable single-cycle interconnection network for Shared-L1 processor clusters	173
A Tightly-Coupled Multi-Core Cluster with Shared-Memory HW Accelerators	173
Fine-Grained Power and Body-Bias Control for Near-Threshold Deep Sub-Micron CMOS Circuits	168
A Multi-banked Shared-L1 Cache Architecture for Tightly Coupled Processor Clusters	167
Automatic synthesis of near-threshold circuits with fine-grained performance tunability	158
Architecture support for tightly-coupled multi-core clusters with shared-memory HW accelerators	155
ReliNoC: A reliable network for priority-based on-chip communication	152
A shared-FPU architecture for ultra-low power MPSoCs, Proceedings of the ACM International Conference on Computing Frontiers - CF '13	151
A new physical routing approach for robust bundled signaling on NoC links	151
A distributed and topology-agnostic approach for on-line NoC testing	148
Robust Near-Threshold Design With Fine-Grained Performance Tunability	139
Row-based FBB: A design-time optimization for post-silicon tunable circuits	135
Moonrake chip - GALS demonstrator in 40 nm CMOS technology	135
Variation-Tolerant Architecture for Ultra Low Power Shared-L1 Processor Clusters	133
Totale	2.314

	Totale	Lug	Ago	Sett	Ott	Nov	Dic	Gen	Feb	Mar	Apr	Mag	Giu
2019/2020	530	67	14	5	55	54	52	62	66	82	29	15	29
2020/2021	294	46	17	18	8	15	4	5	15	30	8	9	119
2021/2022	892	106	6	99	80	117	83	80	77	87	21	67	69
2022/2023	385	52	78	22	28	11	24	15	22	71	3	44	15
2023/2024	62	9	16	6	3	5	17	3	1	0	1	0	1
Totale													2.314

CRIS Current Research Information System