statistiche ricercatore

Nome	#
A resilient architecture for low latency communication in shared-L1 processor clusters	194
A Tightly-Coupled Multi-Core Cluster with Shared-Memory HW Accelerators	189
A fully-synthesizable single-cycle interconnection network for Shared-L1 processor clusters	183
A Multi-banked Shared-L1 Cache Architecture for Tightly Coupled Processor Clusters	182
Fine-Grained Power and Body-Bias Control for Near-Threshold Deep Sub-Micron CMOS Circuits	178
Architecture support for tightly-coupled multi-core clusters with shared-memory HW accelerators	174
A new physical routing approach for robust bundled signaling on NoC links	170
Automatic synthesis of near-threshold circuits with fine-grained performance tunability	168
A distributed and topology-agnostic approach for on-line NoC testing	165
ReliNoC: A reliable network for priority-based on-chip communication	165
A shared-FPU architecture for ultra-low power MPSoCs, Proceedings of the ACM International Conference on Computing Frontiers - CF '13	164
Robust Near-Threshold Design With Fine-Grained Performance Tunability	156
Moonrake chip - GALS demonstrator in 40 nm CMOS technology	148
Variation-Tolerant Architecture for Ultra Low Power Shared-L1 Processor Clusters	145
Row-based FBB: A design-time optimization for post-silicon tunable circuits	144
Totale	2.525

	Totale	Lug	Ago	Sett	Ott	Nov	Dic	Gen	Feb	Mar	Apr	Mag	Giu
2019/2020	221	0	0	0	0	0	0	0	66	82	29	15	29
2020/2021	294	46	17	18	8	15	4	5	15	30	8	9	119
2021/2022	892	106	6	99	80	117	83	80	77	87	21	67	69
2022/2023	385	52	78	22	28	11	24	15	22	71	3	44	15
2023/2024	62	9	16	6	3	5	17	3	1	0	1	0	1
2024/2025	211	14	71	31	7	70	6	12	0	0	0	0	0
Totale													2.525

CRIS Current Research Information System