In this work we propose a shared floating point unit (FPU) architecture for ultra low power (ULP) system on chips operating at near threshold voltage (NTV). Since high-performance FP units (FPUs) are large and complex, but their utilization is relatively low, adding one FPU per each core in a ULP multicore is costly and power hungry. In our approach, we share a few FPUs among all the cores in the system. This increases the utilization of FPUs leading to an energy-efficient design. As a part of our approach, we propose two different FPU allocation techniques: optimal and random. Experimental results demonstrate that compared to a traditional private-FPU approach, our technique in a multicore system with 8 processors and 2 shared FPUs can increase the performance/(area*power) by 5× for applications with 10% FP operations and by 2.5× for applications with 25% FP operations

A shared-FPU architecture for ultra-low power MPSoCs, Proceedings of the ACM International Conference on Computing Frontiers - CF '13 / Mohammad Reza Kakoee;Igor Loi;Luca Benini. - STAMPA. - (2013), pp. 1-8. (Intervento presentato al convegno 2013 ACM International Conference on Computing Frontiers, CF 2013 tenutosi a Ischia; Italy nel May 14-16 2013) [10.1145/2482767.2482772].

A shared-FPU architecture for ultra-low power MPSoCs, Proceedings of the ACM International Conference on Computing Frontiers - CF '13

KAKOEE, MOHAMMAD REZA;LOI, IGOR;BENINI, LUCA
2013

Abstract

In this work we propose a shared floating point unit (FPU) architecture for ultra low power (ULP) system on chips operating at near threshold voltage (NTV). Since high-performance FP units (FPUs) are large and complex, but their utilization is relatively low, adding one FPU per each core in a ULP multicore is costly and power hungry. In our approach, we share a few FPUs among all the cores in the system. This increases the utilization of FPUs leading to an energy-efficient design. As a part of our approach, we propose two different FPU allocation techniques: optimal and random. Experimental results demonstrate that compared to a traditional private-FPU approach, our technique in a multicore system with 8 processors and 2 shared FPUs can increase the performance/(area*power) by 5× for applications with 10% FP operations and by 2.5× for applications with 25% FP operations
2013
Proceedings of the ACM International Conference on Computing Frontiers - CF '13
1
8
A shared-FPU architecture for ultra-low power MPSoCs, Proceedings of the ACM International Conference on Computing Frontiers - CF '13 / Mohammad Reza Kakoee;Igor Loi;Luca Benini. - STAMPA. - (2013), pp. 1-8. (Intervento presentato al convegno 2013 ACM International Conference on Computing Frontiers, CF 2013 tenutosi a Ischia; Italy nel May 14-16 2013) [10.1145/2482767.2482772].
Mohammad Reza Kakoee;Igor Loi;Luca Benini
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11585/306758
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