Tightly coupling hardware accelerators with processors is a well-known approach for boosting the efficiency of MPSoC platforms. The key design challenges in this area are: (i) streamlining accelerator definition and instantiation and (ii) developing architectural templates and run-time techniques for minimizing the cost of communication and synchronization between processors and accelerators. In this paper we present an architecture featuring tightly-coupled processors and hardware processing units (HWPU), with zero-copy communication. We also provide a simple programming API, which simplifies the process of offloading jobs to HWPUs.
M. Dehyadegari, A. Marongiu, M. R. Kakoee, L. Benini, S. Mohammadi, N. Yazdani (2012). A Tightly-Coupled Multi-Core Cluster with Shared-Memory HW Accelerators. NEW YORK : IEEE Press [10.1109/SAMOS.2012.6404162].
A Tightly-Coupled Multi-Core Cluster with Shared-Memory HW Accelerators
MARONGIU, ANDREA;KAKOEE, MOHAMMAD REZA;BENINI, LUCA;
2012
Abstract
Tightly coupling hardware accelerators with processors is a well-known approach for boosting the efficiency of MPSoC platforms. The key design challenges in this area are: (i) streamlining accelerator definition and instantiation and (ii) developing architectural templates and run-time techniques for minimizing the cost of communication and synchronization between processors and accelerators. In this paper we present an architecture featuring tightly-coupled processors and hardware processing units (HWPU), with zero-copy communication. We also provide a simple programming API, which simplifies the process of offloading jobs to HWPUs.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
