The reliability of networks-on-chip (NoC) is threatened by low yield and device wearout in aggressively scaled technology nodes. We propose ReliNoC, a network-on-chip architecture which can withstand failures, while maintaining not only basic connectivity, but also quality-of-service support based on packet priorities. Our network leverages a dual physical channel switch architecture which removes the control overhead of virtual channels (VCs) and utilizes the inherent redundancy within the 2-channel switch to provide spares for faulty elements. Experimental results show that ReliNoC provides 1.5 to 3 times better network physical connectivity in presence of several faults, and reduces the latency of both high and low priority traffic by 30 to 50%, compared to a traditional VC architecture. Moreover, it can tolerate up to 50 faults within an 8×8 mesh at only 10 and 40% latency overhead on control and data packets for PARSEC traces. Synthesis results show that our reliable architecture incurs only 13% area overhead on the baseline 2-channel switch.

Kakoee M.R. , Bertacco V. , Benini L. (2011). ReliNoC: A reliable network for priority-based on-chip communication. New York : IEEE Press [10.1109/DATE.2011.5763112].

ReliNoC: A reliable network for priority-based on-chip communication

KAKOEE, MOHAMMAD REZA;BENINI, LUCA
2011

Abstract

The reliability of networks-on-chip (NoC) is threatened by low yield and device wearout in aggressively scaled technology nodes. We propose ReliNoC, a network-on-chip architecture which can withstand failures, while maintaining not only basic connectivity, but also quality-of-service support based on packet priorities. Our network leverages a dual physical channel switch architecture which removes the control overhead of virtual channels (VCs) and utilizes the inherent redundancy within the 2-channel switch to provide spares for faulty elements. Experimental results show that ReliNoC provides 1.5 to 3 times better network physical connectivity in presence of several faults, and reduces the latency of both high and low priority traffic by 30 to 50%, compared to a traditional VC architecture. Moreover, it can tolerate up to 50 faults within an 8×8 mesh at only 10 and 40% latency overhead on control and data packets for PARSEC traces. Synthesis results show that our reliable architecture incurs only 13% area overhead on the baseline 2-channel switch.
2011
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2011
1
6
Kakoee M.R. , Bertacco V. , Benini L. (2011). ReliNoC: A reliable network for priority-based on-chip communication. New York : IEEE Press [10.1109/DATE.2011.5763112].
Kakoee M.R. ; Bertacco V. ; Benini L.
File in questo prodotto:
Eventuali allegati, non sono esposti

I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.

Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11585/108908
 Attenzione

Attenzione! I dati visualizzati non sono stati sottoposti a validazione da parte dell'ateneo

Citazioni
  • ???jsp.display-item.citation.pmc??? ND
  • Scopus 30
  • ???jsp.display-item.citation.isi??? 2
social impact