Circuit variabilityhasadverseconsequencesondesignpredictabilityandyieldinNanometerCMOS. Post-fabricationtuningapproacheshavebeentargetedinanumberofrecentworkstomitigatethis problem.AdaptiveBodyBias(ABB)isoneofthemostsuccessfultuningknobsinusetodayinhigh- performancecustomdesign.Throughforwardbodybias(FBB),thethresholdvoltageoftheCMOS devices canbereducedafterfabricationtobringtheslowdiesbackwithintherangeofacceptable specs. FBBisusuallyappliedwithaverycoarsegranularityatthepriceofasignificantlyincreased leakagepower.Weproposeanovel,fine-grainedFBBschemeonrow-basedstandardcelllayoutthat enablesselectiveforwardbodybiasingofthoserowsthatcontainmosttimingcriticalgates,thereby reducingleakagepoweroverhead.Thisstyleisfullycompatiblewithstate-of-the-artcommercial physicaldesignflowsandimposesminimalareablow-up.Itcanbeappliedwithoutanyplacement disruptiononafullyplaceddesign.Benchmarkresultsshowlargeleakagepowersavingswitha maximumsavingsof61%incaseof18%compensationin45nmand93%incaseof10%compensation in 32nmwithrespecttoblock-levelapproaches
M. R. Kakoee, A. Sathanur, A. Pullini, L. Benini (2012). Row-based FBB: A design-time optimization for post-silicon tunable circuits. MICROELECTRONICS JOURNAL, 43(7), 456-465 [10.1016/j.mejo.2012.04.001].
Row-based FBB: A design-time optimization for post-silicon tunable circuits
KAKOEE, MOHAMMAD REZA;PULLINI, ANTONIO;BENINI, LUCA
2012
Abstract
Circuit variabilityhasadverseconsequencesondesignpredictabilityandyieldinNanometerCMOS. Post-fabricationtuningapproacheshavebeentargetedinanumberofrecentworkstomitigatethis problem.AdaptiveBodyBias(ABB)isoneofthemostsuccessfultuningknobsinusetodayinhigh- performancecustomdesign.Throughforwardbodybias(FBB),thethresholdvoltageoftheCMOS devices canbereducedafterfabricationtobringtheslowdiesbackwithintherangeofacceptable specs. FBBisusuallyappliedwithaverycoarsegranularityatthepriceofasignificantlyincreased leakagepower.Weproposeanovel,fine-grainedFBBschemeonrow-basedstandardcelllayoutthat enablesselectiveforwardbodybiasingofthoserowsthatcontainmosttimingcriticalgates,thereby reducingleakagepoweroverhead.Thisstyleisfullycompatiblewithstate-of-the-artcommercial physicaldesignflowsandimposesminimalareablow-up.Itcanbeappliedwithoutanyplacement disruptiononafullyplaceddesign.Benchmarkresultsshowlargeleakagepowersavingswitha maximumsavingsof61%incaseof18%compensationin45nmand93%incaseof10%compensation in 32nmwithrespecttoblock-levelapproachesI documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
