In this work we investigate the electrostatics of three multi-gate device structures, namely the rectangular GAA-FET, the tri-gate FinFET and the Pi-gate FET, all of them at three different miniaturization limits corresponding to the 90, 65 and 45 nm technology nodes of the ITRS. In doing so, we solve both the classical Poisson equation and the coupled Schroedinger-Poisson equations within the device cross sections, and compare the classical and quantum-mechanical (QM) solutions. This comparison highlights the qualitative and quantitative discrepancies between the two models, both in terms of charge distribution and device performance. These differences turn out to be very relevant for all device structures, and increase as the device size is scaled down. Thus, the main conclusion of this study is that accounting for quantum-mechanical effects in device simulation is essential for a realistic prediction of the device threshold voltage, inversion-layer charge and gate capacitance.

A quantum mechanical analysis of the electrostatics in multiple-gate FETs

GNANI, ELENA;REGGIANI, SUSANNA;RUDAN, MASSIMO;BACCARANI, GIORGIO
2005

Abstract

In this work we investigate the electrostatics of three multi-gate device structures, namely the rectangular GAA-FET, the tri-gate FinFET and the Pi-gate FET, all of them at three different miniaturization limits corresponding to the 90, 65 and 45 nm technology nodes of the ITRS. In doing so, we solve both the classical Poisson equation and the coupled Schroedinger-Poisson equations within the device cross sections, and compare the classical and quantum-mechanical (QM) solutions. This comparison highlights the qualitative and quantitative discrepancies between the two models, both in terms of charge distribution and device performance. These differences turn out to be very relevant for all device structures, and increase as the device size is scaled down. Thus, the main conclusion of this study is that accounting for quantum-mechanical effects in device simulation is essential for a realistic prediction of the device threshold voltage, inversion-layer charge and gate capacitance.
International Conference on Simulation of Semiconductor Processes and Devices (SISPAD 2005)
291
294
E. Gnani; S. Reggiani; M. Rudan; G. Baccarani
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11585/9911
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