Role of the GaN-on-Si Epi-Stack on Δ RONCaused by Back-Gating Stress

This article reports an in-depth analysis of the ON-resistance drift induced by storage/release mechanisms occurring in the buffer of GaN-on-Si power devices. The role of both stress condition (bias, temperature, and stress time) and buffer's epi-stack composition on the ON-resistance drift has been analyzed by means of back-gating current deep-level transient spectroscopy (I-DLTS). The results reveal two competing mechanisms: 1) a faster one related to acceptor defects and sensitive to the thickness of the carbon-doped GaN back-barrier (C:GaN) and superlattice (SL) layers and 2) a slower one ascribed to hole accumulation at the C:GaN/SL interface, independent of the thickness of the epi-stack. The temperature, stress bias, and stress time dependence of such mechanisms, often overlapping, have been investigated by adopting a genetic algorithm.