A new analytical model for carrier mobility in silicon is presented, which is strongly oriented to CAD and suitable for implementation in device simulators. The effects of the electric field, temperature, and doping concentration are accounted for. In particular, the model unifies the descriptions of majority- and minority-carrier mobility and includes the full temperature dependence. The effects of a high longitudinal field are included in the conventional velocity-saturation form; the doping dependence is also incorporated in the latter. The model has been worked out starting from a preliminary investigation using a Boltzmann solver, and has been validated by a number of comparisons with published experiments on silicon.

Reggiani S., Valdinoci M., Colalongo L., Rudan M., Baccarani G. (2000). Analytical, temperature-dependent model for majority- and minority-carrier mobility in silicon devices. VLSI DESIGN, 10(4), 467-483 [10.1155/2000/52147].

Analytical, temperature-dependent model for majority- and minority-carrier mobility in silicon devices

Reggiani S.;Valdinoci M.;Colalongo L.;Rudan M.;Baccarani G.
2000

Abstract

A new analytical model for carrier mobility in silicon is presented, which is strongly oriented to CAD and suitable for implementation in device simulators. The effects of the electric field, temperature, and doping concentration are accounted for. In particular, the model unifies the descriptions of majority- and minority-carrier mobility and includes the full temperature dependence. The effects of a high longitudinal field are included in the conventional velocity-saturation form; the doping dependence is also incorporated in the latter. The model has been worked out starting from a preliminary investigation using a Boltzmann solver, and has been validated by a number of comparisons with published experiments on silicon.
2000
Reggiani S., Valdinoci M., Colalongo L., Rudan M., Baccarani G. (2000). Analytical, temperature-dependent model for majority- and minority-carrier mobility in silicon devices. VLSI DESIGN, 10(4), 467-483 [10.1155/2000/52147].
Reggiani S.; Valdinoci M.; Colalongo L.; Rudan M.; Baccarani G.
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11585/895727
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