Explanation of the rugged LDMOS behavior by means of numerical analysis

In this paper, a numerical investigation on the behavior of a rugged LDMOS transistor operating in the high current–voltage pulsed regime is carried out with the aim of clarifying the physical origin of the current “enhancement” that is visible in the output characteristics at high drain and gate biases. The investigation shows that the output characteristics are significantly affected by the “quasi-saturation” effect at low drain voltages. The impact-ionization rate in the drain extension at high drain voltages reduces the series resistance of the drift region and, hence, raises the electrostatic potential near the channel end, thus driving the intrinsic MOSFET into a saturation condition. The analysis provides a clear insight on the “quasi-saturation” and current “enhancement” effects, which is instrumental for the development of compact models that are particularly useful for circuit-design tools.