Steep-slope devices: Prospects and challenges

In this work, an overview is given on the prospects and challenges of two novel device concepts, namely the Tunnel FET (TFET) and the Superlattice FET (SL-FET). The optimization effort of homo- and hetero-junction TFETs carried out so far shows that these devices can provide an advantage over CMOS FETs only for very-low power and low-performance niche applications, so long as the supply voltage is scaled below 300 mV. The required materials for homojunction TFETs are low bandgap semiconductors, such as InAs and InGaAs; for heterojunction TFETs the best semiconductor pair appears to be (Al)GaSb-InAs. Several technological problems are still unsolved: poor quality of the oxide interface with III-V materials and device variability are probably the most important. The SL-FET represents in principle a better device concept, as it provides outstanding performance and meets nearly all targets of the high performance (HP), low operating power (LOP) and low standby power (LSTP) of the ITRS at VDD = 0.4 V. A suitably-designed InGaAs-InAlAs SL-FET has turned out to provide the best simulation results. However, the fabrication process of SL-FETs is much more complex, as it requires molecular epitaxy to deposit multiple layers with a very strict control of their nanometric thickness. Besides, vertical devices can pose unexpected problems as far as layout organization and parasitics are concerned.