This chapter introduces integrated power devices and their reliability issues. The lateral double-diffused MOS (LDMOS) transistors are widely used in mixed-signal circuit design as integrated high-voltage switches and drivers. The LDMOS with shallow-trench isolation (STI) is the device of choice to achieve voltage and current capability integrated in the basic CMOS processes. The electrical characteristics of the STI-based LDMOS transistors are reviewed over an extended range of operating conditions through experiments and numerical analysis. The high electric-field regime is explained to the purpose of investigating the effects on the electrical safe operating area (SOA) and device reliability under hot-carrier stress (HCS) conditions. A review of the HCS modeling is addressed to the purpose of understanding the degradation kinetics and mechanisms. TCAD simulations of HCS degradation are finally reported to explain the HCS effects on a wide range of biases and temperatures, confirming the experimental results.
Reggiani, S., Barone, G., Gnani, E., Gnudi, A., Baccarani, G., Poli, S., et al. (2015). Characterization and modeling of high-voltage LDMOS transistors. Cham, Switzerland : Springer International Publishing [10.1007/978-3-319-08994-2_11].
Characterization and modeling of high-voltage LDMOS transistors
REGGIANI, SUSANNA;BARONE, GAETANO;GNANI, ELENA;GNUDI, ANTONIO;BACCARANI, GIORGIO;
2015
Abstract
This chapter introduces integrated power devices and their reliability issues. The lateral double-diffused MOS (LDMOS) transistors are widely used in mixed-signal circuit design as integrated high-voltage switches and drivers. The LDMOS with shallow-trench isolation (STI) is the device of choice to achieve voltage and current capability integrated in the basic CMOS processes. The electrical characteristics of the STI-based LDMOS transistors are reviewed over an extended range of operating conditions through experiments and numerical analysis. The high electric-field regime is explained to the purpose of investigating the effects on the electrical safe operating area (SOA) and device reliability under hot-carrier stress (HCS) conditions. A review of the HCS modeling is addressed to the purpose of understanding the degradation kinetics and mechanisms. TCAD simulations of HCS degradation are finally reported to explain the HCS effects on a wide range of biases and temperatures, confirming the experimental results.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
