In this work full-quantum simulations have been employed to devise and optimize both impurity-doped (ID) and electrostatically-doped (ED) superlattice FETs (SL-FETs). A sensitivity investigation to technological and design parameters has been carried out, showing a relatively-low sensitivity to changes of most device parameters. Results at a reduced power supply VDD=0.4V are compared with the ITRS specs projected to year 2022. Benchmarking highlights the potential of the proposed ED InGaAs/InAlAs SL-FET to perform up to 1.2× faster than HP specs with 5× lower energy-delay product. This device is thus expected to be a good candidate for the post-CMOS era.
Pasquale, M., Elena, G., Antonio, G., Susanna, R., Giorgio, B. (2014). Design and optimization of impurity- and electrostatically-doped superlattice FETs to meet all the ITRS power targets at VDD=0.4V. SOLID-STATE ELECTRONICS, 101, 70-78 [10.1016/j.sse.2014.06.020].
Design and optimization of impurity- and electrostatically-doped superlattice FETs to meet all the ITRS power targets at VDD=0.4V
MAIORANO, PASQUALE;GNANI, ELENA;GNUDI, ANTONIO;REGGIANI, SUSANNA;BACCARANI, GIORGIO
2014
Abstract
In this work full-quantum simulations have been employed to devise and optimize both impurity-doped (ID) and electrostatically-doped (ED) superlattice FETs (SL-FETs). A sensitivity investigation to technological and design parameters has been carried out, showing a relatively-low sensitivity to changes of most device parameters. Results at a reduced power supply VDD=0.4V are compared with the ITRS specs projected to year 2022. Benchmarking highlights the potential of the proposed ED InGaAs/InAlAs SL-FET to perform up to 1.2× faster than HP specs with 5× lower energy-delay product. This device is thus expected to be a good candidate for the post-CMOS era.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
