In this paper we analyze LF noise in trench-gate power MOSFETs to investigate the effect of negative bias temperature stress on the gate dielectric quality. We study how the amount of stress time influences both the threshold voltage and the trap density within gate oxide. After the stress, recovery conditions are applied to the device and its properties, in terms of threshold voltage, on-current and trap density, are analyzed. The present study allows to identify permanent and recoverable mechanisms associated to the applied stress.
P. Magnone, G. Barletta, P.A. Traverso, A. Magri, E. Sangiorgi, C. Fiegna (2014). Understanding negative bias temperature stress in p-channel trench-gate power MOSFETs by low-frequency noise measurement2014 IEEE 26th International Symposium on Power Semiconductor Devices & IC's (ISPSD). Institute of Electrical and Electronics Engineers Inc. [10.1109/ISPSD.2014.6856001].
Understanding negative bias temperature stress in p-channel trench-gate power MOSFETs by low-frequency noise measurement2014 IEEE 26th International Symposium on Power Semiconductor Devices & IC's (ISPSD)
MAGNONE, PAOLO;TRAVERSO, PIER ANDREA;SANGIORGI, ENRICO;FIEGNA, CLAUDIO
2014
Abstract
In this paper we analyze LF noise in trench-gate power MOSFETs to investigate the effect of negative bias temperature stress on the gate dielectric quality. We study how the amount of stress time influences both the threshold voltage and the trap density within gate oxide. After the stress, recovery conditions are applied to the device and its properties, in terms of threshold voltage, on-current and trap density, are analyzed. The present study allows to identify permanent and recoverable mechanisms associated to the applied stress.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
